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Implement carry for subtract/add for mips16
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166755 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -194,6 +194,10 @@ class FRR16_ins<bits<5> f, string asmstr, InstrItinClass itin> :
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!strconcat(asmstr, "\t$rx, $ry"), [], itin> {
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}
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class FRRTR16_ins<bits<5> f, string asmstr, InstrItinClass itin> :
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FRR16<f, (outs CPU16Regs:$rz), (ins CPU16Regs:$rx, CPU16Regs:$ry),
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!strconcat(asmstr, "\t$rx, $ry\n\tmove\t$rz, $$t8"), [], itin> ;
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//
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// maybe refactor but need a $zero as a dummy first parameter
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//
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@ -816,6 +820,9 @@ def SltCCRxRy16: FCCRR16_ins<0b00010, "slt", IIAlu>;
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// Purpose: Set on Less Than Unsigned
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// To record the result of an unsigned less-than comparison.
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//
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def SltuRxRyRz16: FRRTR16_ins<0b00011, "sltu", IIAlu> {
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let isCodeGenOnly=1;
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}
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def SltuCCRxRy16: FCCRR16_ins<0b00011, "sltu", IIAlu>;
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@ -976,6 +983,14 @@ def : Mips16Pat<(i32 imm:$imm),
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(OrRxRxRy16 (SllX16 (LiRxImmX16 (HI16 imm:$imm)), 16),
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(LiRxImmX16 (LO16 imm:$imm)))>;
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// Carry MipsPatterns
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def : Mips16Pat<(subc CPU16Regs:$lhs, CPU16Regs:$rhs),
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(SubuRxRyRz16 CPU16Regs:$lhs, CPU16Regs:$rhs)>;
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def : Mips16Pat<(addc CPU16Regs:$lhs, CPU16Regs:$rhs),
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(AdduRxRyRz16 CPU16Regs:$lhs, CPU16Regs:$rhs)>;
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def : Mips16Pat<(addc CPU16Regs:$src, immSExt16:$imm),
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(AddiuRxRxImmX16 CPU16Regs:$src, imm:$imm)>;
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//
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// Some branch conditional patterns are not generated by llvm at this time.
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// Some are for seemingly arbitrary reasons not used: i.e. with signed number
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@ -413,6 +413,7 @@ SDNode* MipsDAGToDAGISel::Select(SDNode *Node) {
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case ISD::SUBE:
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case ISD::ADDE: {
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bool inMips16Mode = Subtarget.inMips16Mode();
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SDValue InFlag = Node->getOperand(2), CmpLHS;
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unsigned Opc = InFlag.getOpcode(); (void)Opc;
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assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
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@ -422,10 +423,16 @@ SDNode* MipsDAGToDAGISel::Select(SDNode *Node) {
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unsigned MOp;
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if (Opcode == ISD::ADDE) {
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CmpLHS = InFlag.getValue(0);
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MOp = Mips::ADDu;
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if (inMips16Mode)
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MOp = Mips::AdduRxRyRz16;
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else
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MOp = Mips::ADDu;
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} else {
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CmpLHS = InFlag.getOperand(0);
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MOp = Mips::SUBu;
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if (inMips16Mode)
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MOp = Mips::SubuRxRyRz16;
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else
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MOp = Mips::SUBu;
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}
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SDValue Ops[] = { CmpLHS, InFlag.getOperand(1) };
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@ -434,8 +441,11 @@ SDNode* MipsDAGToDAGISel::Select(SDNode *Node) {
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SDValue RHS = Node->getOperand(1);
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EVT VT = LHS.getValueType();
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SDNode *Carry = CurDAG->getMachineNode(Mips::SLTu, dl, VT, Ops, 2);
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SDNode *AddCarry = CurDAG->getMachineNode(Mips::ADDu, dl, VT,
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unsigned Sltu_op = inMips16Mode? Mips::SltuRxRyRz16: Mips::SLTu;
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SDNode *Carry = CurDAG->getMachineNode(Sltu_op, dl, VT, Ops, 2);
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unsigned Addu_op = inMips16Mode? Mips::AdduRxRyRz16 : Mips::ADDu;
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SDNode *AddCarry = CurDAG->getMachineNode(Addu_op, dl, VT,
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SDValue(Carry,0), RHS);
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return CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue,
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51
test/CodeGen/Mips/llcarry.ll
Normal file
51
test/CodeGen/Mips/llcarry.ll
Normal file
@ -0,0 +1,51 @@
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; RUN: llc -march=mipsel -mcpu=mips16 -relocation-model=pic -O3 < %s | FileCheck %s -check-prefix=16
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@i = global i64 4294967295, align 8
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@j = global i64 15, align 8
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@ii = global i64 4294967295, align 8
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@k = common global i64 0, align 8
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@l = common global i64 0, align 8
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@m = common global i64 0, align 8
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define void @test1() nounwind {
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entry:
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%0 = load i64* @i, align 8
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%1 = load i64* @j, align 8
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%add = add nsw i64 %1, %0
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store i64 %add, i64* @k, align 8
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; 16: addu ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
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; 16: sltu ${{[0-9]+}}, ${{[0-9]+}}
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; 16: move ${{[0-9]+}}, $t8
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; 16: addu ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
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; 16: addu ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
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ret void
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}
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define void @test2() nounwind {
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entry:
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%0 = load i64* @i, align 8
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%1 = load i64* @j, align 8
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%sub = sub nsw i64 %0, %1
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; 16: subu ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
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; 16: sltu ${{[0-9]+}}, ${{[0-9]+}}
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; 16: move ${{[0-9]+}}, $t8
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; 16: addu ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
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; 16: subu ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
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store i64 %sub, i64* @l, align 8
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ret void
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}
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define void @test3() nounwind {
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entry:
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%0 = load i64* @ii, align 8
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%add = add nsw i64 %0, 15
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; 16: addiu ${{[0-9]+}}, 15
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; 16: sltu ${{[0-9]+}}, ${{[0-9]+}}
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; 16: move ${{[0-9]+}}, $t8
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; 16: addu ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
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; 16: addu ${{[0-9]+}}, ${{[0-9]+}}, ${{[0-9]+}}
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store i64 %add, i64* @m, align 8
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ret void
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}
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