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Compile this:

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short test4(unsigned X) {
  return (X >> 16);
}

to:

_test4:
        movl 4(%esp), %eax
        sarl $16, %eax
        ret

instead of:

_test4:
        movl $-65536, %eax
        andl 4(%esp), %eax
        sarl $16, %eax
        ret


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28171 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2006-05-08 20:51:54 +00:00
parent fcf64a91d6
commit a850446a0b
1 changed files with 5 additions and 0 deletions
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5
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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@ -1575,6 +1575,11 @@ SDOperand DAGCombiner::visitSRA(SDNode *N) {
}
}
// Simplify, based on bits shifted out of the LHS.
if (N1C && SimplifyDemandedBits(SDOperand(N, 0)))
return SDOperand(N, 0);
// If the sign bit is known to be zero, switch this to a SRL.
if (TLI.MaskedValueIsZero(N0, MVT::getIntVTSignBit(VT)))
return DAG.getNode(ISD::SRL, VT, N0, N1);