From a88ea03bf22ba098f1b7d3471d98f3303dcbd33f Mon Sep 17 00:00:00 2001 From: Owen Anderson Date: Tue, 26 Oct 2010 17:40:54 +0000 Subject: [PATCH] Add NEON encodings for vmov and vmvn of immediates. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117374 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMInstrFormats.td | 10 ++ lib/Target/ARM/ARMInstrNEON.td | 42 +++++-- test/MC/ARM/neon-bitwise-encoding.ll | 1 - test/MC/ARM/neon-mov-encoding.ll | 169 +++++++++++++++++++++++++++ 4 files changed, 209 insertions(+), 13 deletions(-) create mode 100644 test/MC/ARM/neon-mov-encoding.ll diff --git a/lib/Target/ARM/ARMInstrFormats.td b/lib/Target/ARM/ARMInstrFormats.td index 3a1fec7a3a7..3d43edba728 100644 --- a/lib/Target/ARM/ARMInstrFormats.td +++ b/lib/Target/ARM/ARMInstrFormats.td @@ -1683,6 +1683,16 @@ class N1ModImm op21_19, bits<4> op11_8, bit op7, bit op6, let Inst{6} = op6; let Inst{5} = op5; let Inst{4} = op4; + + // Instruction operands. + bits<5> Vd; + bits<13> SIMM; + + let Inst{15-12} = Vd{3-0}; + let Inst{22} = Vd{4}; + let Inst{24} = SIMM{7}; + let Inst{18-16} = SIMM{6-4}; + let Inst{3-0} = SIMM{3-0}; } // NEON 2 vector register format. diff --git a/lib/Target/ARM/ARMInstrNEON.td b/lib/Target/ARM/ARMInstrNEON.td index a38b482fcc0..85576a552fe 100644 --- a/lib/Target/ARM/ARMInstrNEON.td +++ b/lib/Target/ARM/ARMInstrNEON.td @@ -2899,26 +2899,34 @@ def VORNq : N3VX<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$dst), // VMVN : Vector Bitwise NOT (Immediate) let isReMaterializable = 1 in { -// FIXME: This instruction's encoding MAY NOT BE correct. + def VMVNv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 1, 1, (outs DPR:$dst), (ins nModImm:$SIMM), IIC_VMOVImm, "vmvn", "i16", "$dst, $SIMM", "", - [(set DPR:$dst, (v4i16 (NEONvmvnImm timm:$SIMM)))]>; -// FIXME: This instruction's encoding MAY NOT BE correct. + [(set DPR:$dst, (v4i16 (NEONvmvnImm timm:$SIMM)))]> { + let Inst{9} = SIMM{9}; +} + def VMVNv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 1, 1, (outs QPR:$dst), (ins nModImm:$SIMM), IIC_VMOVImm, "vmvn", "i16", "$dst, $SIMM", "", - [(set QPR:$dst, (v8i16 (NEONvmvnImm timm:$SIMM)))]>; -// FIXME: This instruction's encoding MAY NOT BE correct. + [(set QPR:$dst, (v8i16 (NEONvmvnImm timm:$SIMM)))]> { + let Inst{9} = SIMM{9}; +} + def VMVNv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 1, 1, (outs DPR:$dst), (ins nModImm:$SIMM), IIC_VMOVImm, "vmvn", "i32", "$dst, $SIMM", "", - [(set DPR:$dst, (v2i32 (NEONvmvnImm timm:$SIMM)))]>; -// FIXME: This instruction's encoding MAY NOT BE correct. + [(set DPR:$dst, (v2i32 (NEONvmvnImm timm:$SIMM)))]> { + let Inst{11-8} = SIMM{11-8}; +} + def VMVNv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 1, 1, (outs QPR:$dst), (ins nModImm:$SIMM), IIC_VMOVImm, "vmvn", "i32", "$dst, $SIMM", "", - [(set QPR:$dst, (v4i32 (NEONvmvnImm timm:$SIMM)))]>; + [(set QPR:$dst, (v4i32 (NEONvmvnImm timm:$SIMM)))]> { + let Inst{11-8} = SIMM{11-8}; +} } // VMVN : Vector Bitwise NOT @@ -3387,20 +3395,30 @@ def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$dst), def VMOVv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 0, 1, (outs DPR:$dst), (ins nModImm:$SIMM), IIC_VMOVImm, "vmov", "i16", "$dst, $SIMM", "", - [(set DPR:$dst, (v4i16 (NEONvmovImm timm:$SIMM)))]>; + [(set DPR:$dst, (v4i16 (NEONvmovImm timm:$SIMM)))]> { + let Inst{9} = SIMM{9}; +} + def VMOVv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 0, 1, (outs QPR:$dst), (ins nModImm:$SIMM), IIC_VMOVImm, "vmov", "i16", "$dst, $SIMM", "", - [(set QPR:$dst, (v8i16 (NEONvmovImm timm:$SIMM)))]>; + [(set QPR:$dst, (v8i16 (NEONvmovImm timm:$SIMM)))]> { + let Inst{9} = SIMM{9}; +} def VMOVv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 0, 1, (outs DPR:$dst), (ins nModImm:$SIMM), IIC_VMOVImm, "vmov", "i32", "$dst, $SIMM", "", - [(set DPR:$dst, (v2i32 (NEONvmovImm timm:$SIMM)))]>; + [(set DPR:$dst, (v2i32 (NEONvmovImm timm:$SIMM)))]> { + let Inst{11-8} = SIMM{11-8}; +} + def VMOVv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 0, 1, (outs QPR:$dst), (ins nModImm:$SIMM), IIC_VMOVImm, "vmov", "i32", "$dst, $SIMM", "", - [(set QPR:$dst, (v4i32 (NEONvmovImm timm:$SIMM)))]>; + [(set QPR:$dst, (v4i32 (NEONvmovImm timm:$SIMM)))]> { + let Inst{11-8} = SIMM{11-8}; +} def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$dst), (ins nModImm:$SIMM), IIC_VMOVImm, diff --git a/test/MC/ARM/neon-bitwise-encoding.ll b/test/MC/ARM/neon-bitwise-encoding.ll index d8e209f23e2..3a3ba9266a8 100644 --- a/test/MC/ARM/neon-bitwise-encoding.ll +++ b/test/MC/ARM/neon-bitwise-encoding.ll @@ -2,7 +2,6 @@ ; FIXME: The following instructions still require testing: ; - vand with immediate, vorr with immediate -; - vmvn of an immediate ; - both vbit and vbif ; CHECK: vand_8xi8 diff --git a/test/MC/ARM/neon-mov-encoding.ll b/test/MC/ARM/neon-mov-encoding.ll new file mode 100644 index 00000000000..68edaed2ef9 --- /dev/null +++ b/test/MC/ARM/neon-mov-encoding.ll @@ -0,0 +1,169 @@ +; RUN: llc -show-mc-encoding -march=arm -mcpu=cortex-a8 -mattr=+neon < %s | FileCheck %s + +; CHECK: vmov_8xi8 +define <8 x i8> @vmov_8xi8() nounwind { +; CHECK: vmov.i8 d16, #0x8 @ encoding: [0x18,0x0e,0xc0,0xf2] + ret <8 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 > +} + +; CHECK: vmov_4xi16a +define <4 x i16> @vmov_4xi16a() nounwind { +; CHECK: vmov.i16 d16, #0x10 @ encoding: [0x10,0x08,0xc1,0xf2] + ret <4 x i16> < i16 16, i16 16, i16 16, i16 16 > +} + +; CHECK: vmov_4xi16b +define <4 x i16> @vmov_4xi16b() nounwind { +; CHECK: vmov.i16 d16, #0x1000 @ encoding: [0x10,0x0a,0xc1,0xf2] + ret <4 x i16> < i16 4096, i16 4096, i16 4096, i16 4096 > +} + +; CHECK: vmov_2xi32a +define <2 x i32> @vmov_2xi32a() nounwind { +; CHECK: vmov.i32 d16, #0x20 @ encoding: [0x10,0x00,0xc2,0xf2] + ret <2 x i32> < i32 32, i32 32 > +} + +; CHECK: vmov_2xi32b +define <2 x i32> @vmov_2xi32b() nounwind { +; CHECK: vmov.i32 d16, #0x2000 @ encoding: [0x10,0x02,0xc2,0xf2] + ret <2 x i32> < i32 8192, i32 8192 > +} + +; CHECK: vmov_2xi32c +define <2 x i32> @vmov_2xi32c() nounwind { +; CHECK: vmov.i32 d16, #0x200000 @ encoding: [0x10,0x04,0xc2,0xf2] + ret <2 x i32> < i32 2097152, i32 2097152 > +} + +; CHECK: vmov_2xi32d +define <2 x i32> @vmov_2xi32d() nounwind { +; CHECK: vmov.i32 d16, #0x20000000 @ encoding: [0x10,0x06,0xc2,0xf2] + ret <2 x i32> < i32 536870912, i32 536870912 > +} + +; CHECK: vmov_2xi32e +define <2 x i32> @vmov_2xi32e() nounwind { +; CHECK: vmov.i32 d16, #0x20FF @ encoding: [0x10,0x0c,0xc2,0xf2] + ret <2 x i32> < i32 8447, i32 8447 > +} + +; CHECK: vmov_2xi32f +define <2 x i32> @vmov_2xi32f() nounwind { +; CHECK: vmov.i32 d16, #0x20FFFF @ encoding: [0x10,0x0d,0xc2,0xf2] + ret <2 x i32> < i32 2162687, i32 2162687 > +} + +; CHECK: vmov_1xi64 +define <1 x i64> @vmov_1xi64() nounwind { +; CHECK: vmov.i64 d16, #0xFF0000FF0000FFFF @ encoding: [0x33,0x0e,0xc1,0xf3] + ret <1 x i64> < i64 18374687574888349695 > +} + +; CHECK: vmov_16xi8 +define <16 x i8> @vmov_16xi8() nounwind { +; CHECK: vmov.i8 q8, #0x8 @ encoding: [0x58,0x0e,0xc0,0xf2] + ret <16 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 > +} + +; CHECK: vmov_8xi16a +define <8 x i16> @vmov_8xi16a() nounwind { +; CHECK: vmov.i16 q8, #0x10 @ encoding: [0x50,0x08,0xc1,0xf2] + ret <8 x i16> < i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16 > +} + +; CHECK: vmov_8xi16b +define <8 x i16> @vmov_8xi16b() nounwind { +; CHECK: vmov.i16 q8, #0x1000 @ encoding: [0x50,0x0a,0xc1,0xf2] + ret <8 x i16> < i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096 > +} + +; CHECK: vmov_4xi32a +define <4 x i32> @vmov_4xi32a() nounwind { +; CHECK: vmov.i32 q8, #0x20 @ encoding: [0x50,0x00,0xc2,0xf2] + ret <4 x i32> < i32 32, i32 32, i32 32, i32 32 > +} + +; CHECK: vmov_4xi32b +define <4 x i32> @vmov_4xi32b() nounwind { +; CHECK: vmov.i32 q8, #0x2000 @ encoding: [0x50,0x02,0xc2,0xf2] + ret <4 x i32> < i32 8192, i32 8192, i32 8192, i32 8192 > +} + +; CHECK: vmov_4xi32c +define <4 x i32> @vmov_4xi32c() nounwind { +; CHECK: vmov.i32 q8, #0x200000 @ encoding: [0x50,0x04,0xc2,0xf2] + ret <4 x i32> < i32 2097152, i32 2097152, i32 2097152, i32 2097152 > +} + +; CHECK: vmov_4xi32d +define <4 x i32> @vmov_4xi32d() nounwind { +; CHECK: vmov.i32 q8, #0x20000000 @ encoding: [0x50,0x06,0xc2,0xf2] + ret <4 x i32> < i32 536870912, i32 536870912, i32 536870912, i32 536870912 > +} + +; CHECK: vmov_4xi32e +define <4 x i32> @vmov_4xi32e() nounwind { +; CHECK: vmov.i32 q8, #0x20FF @ encoding: [0x50,0x0c,0xc2,0xf2] + ret <4 x i32> < i32 8447, i32 8447, i32 8447, i32 8447 > +} + +; CHECK: vmov_4xi32f +define <4 x i32> @vmov_4xi32f() nounwind { +; CHECK: vmov.i32 q8, #0x20FFFF @ encoding: [0x50,0x0d,0xc2,0xf2] + ret <4 x i32> < i32 2162687, i32 2162687, i32 2162687, i32 2162687 > +} + +; CHECK: vmov_2xi64 +define <2 x i64> @vmov_2xi64() nounwind { +; CHECK: vmov.i64 q8, #0xFF0000FF0000FFFF @ encoding: [0x73,0x0e,0xc1,0xf3] + ret <2 x i64> < i64 18374687574888349695, i64 18374687574888349695 > +} + +; CHECK: vmvn_4xi16a +define <4 x i16> @vmvn_4xi16a() nounwind { +; CHECK: vmvn.i16 d16, #0x10 @ encoding: [0x30,0x08,0xc1,0xf2] + ret <4 x i16> < i16 65519, i16 65519, i16 65519, i16 65519 > +} + +; CHECK: vmvn_4xi16b +define <4 x i16> @vmvn_4xi16b() nounwind { +; CHECK: vmvn.i16 d16, #0x1000 @ encoding: [0x30,0x0a,0xc1,0xf2] + ret <4 x i16> < i16 61439, i16 61439, i16 61439, i16 61439 > +} + +; CHECK: vmvn_2xi32a +define <2 x i32> @vmvn_2xi32a() nounwind { +; CHECK: vmvn.i32 d16, #0x20 @ encoding: [0x30,0x00,0xc2,0xf2] + ret <2 x i32> < i32 4294967263, i32 4294967263 > +} + +; CHECK: vmvn_2xi32b +define <2 x i32> @vmvn_2xi32b() nounwind { +; CHECK: vmvn.i32 d16, #0x2000 @ encoding: [0x30,0x02,0xc2,0xf2] + ret <2 x i32> < i32 4294959103, i32 4294959103 > +} + +; CHECK: vmvn_2xi32c +define <2 x i32> @vmvn_2xi32c() nounwind { +; CHECK: vmvn.i32 d16, #0x200000 @ encoding: [0x30,0x04,0xc2,0xf2] + ret <2 x i32> < i32 4292870143, i32 4292870143 > +} + +; CHECK: vmvn_2xi32d +define <2 x i32> @vmvn_2xi32d() nounwind { +; CHECK: vmvn.i32 d16, #0x20000000 @ encoding: [0x30,0x06,0xc2,0xf2] + ret <2 x i32> < i32 3758096383, i32 3758096383 > +} + +; CHECK: vmvn_2xi32e +define <2 x i32> @vmvn_2xi32e() nounwind { +; CHECK: vmvn.i32 d16, #0x20FF @ encoding: [0x30,0x0c,0xc2,0xf2] + ret <2 x i32> < i32 4294958848, i32 4294958848 > +} + +; CHECK: vmvn_2xi32f +define <2 x i32> @vmvn_2xi32f() nounwind { +; CHECK: vmvn.i32 d16, #0x20FFFF @ encoding: [0x30,0x0d,0xc2,0xf2] + ret <2 x i32> < i32 4292804608, i32 4292804608 > +}