6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-02-07 14:33:15 +00:00
Code Issues Projects Releases Wiki Activity

Inline simple comparison which is sparc specific anyway

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@8309 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2003-09-01 20:38:03 +00:00
parent be4063babd
commit a89d8f7468
1 changed files with 45 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

47
lib/Target/SparcV9/SparcV9PeepholeOpts.cpp
View File

@ -10,7 +10,6 @@
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetOptInfo.h"
#include "llvm/BasicBlock.h"
#include "llvm/Pass.h"
@ -42,11 +41,55 @@ DeleteInstruction(MachineBasicBlock& mvec,
//******************* Individual Peephole Optimizations ********************/
//----------------------------------------------------------------------------
// Function: IsUselessCopy
// Decide whether a machine instruction is a redundant copy:
// -- ADD with g0 and result and operand are identical, or
// -- OR with g0 and result and operand are identical, or
// -- FMOVS or FMOVD and result and operand are identical.
// Other cases are possible but very rare that they would be useless copies,
// so it's not worth analyzing them.
//----------------------------------------------------------------------------
static bool IsUselessCopy(const TargetMachine &target, const MachineInstr* MI) {
if (MI->getOpCode() == V9::FMOVS || MI->getOpCode() == V9::FMOVD) {
return (/* both operands are allocated to the same register */
MI->getOperand(0).getAllocatedRegNum() ==
MI->getOperand(1).getAllocatedRegNum());
} else if (MI->getOpCode() == V9::ADDr || MI->getOpCode() == V9::ORr) {
unsigned srcWithDestReg;
for (srcWithDestReg = 0; srcWithDestReg < 2; ++srcWithDestReg)
if (MI->getOperand(srcWithDestReg).hasAllocatedReg() &&
MI->getOperand(srcWithDestReg).getAllocatedRegNum()
== MI->getOperand(2).getAllocatedRegNum())
break;
if (srcWithDestReg == 2)
return false;
else {
/* else source and dest are allocated to the same register */
unsigned otherOp = 1 - srcWithDestReg;
return (/* either operand otherOp is register %g0 */
(MI->getOperand(otherOp).hasAllocatedReg() &&
MI->getOperand(otherOp).getAllocatedRegNum() ==
target.getRegInfo().getZeroRegNum()) ||
/* or operand otherOp == 0 */
(MI->getOperand(otherOp).getType()
== MachineOperand::MO_SignExtendedImmed &&
MI->getOperand(otherOp).getImmedValue() == 0));
}
}
else
return false;
}
inline bool
RemoveUselessCopies(MachineBasicBlock& mvec,
MachineBasicBlock::iterator& BBI,
const TargetMachine& target) {
if (target.getOptInfo().IsUselessCopy(*BBI)) {
if (IsUselessCopy(target, *BBI)) {
DeleteInstruction(mvec, BBI, target);
return true;
}