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R600/SI: Legalize CopyToReg during instruction selection

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The instruction emitter will crash if it encounters a CopyToReg
node with a non-register operand like FrameIndex.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219428 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tom Stellard
2014-10-09 19:06:00 +00:00
parent 80bfef5ce1
commit a8b2e6f4af
4 changed files with 46 additions and 14 deletions
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7
lib/Target/R600/AMDGPUISelDAGToDAG.cpp
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@@ -487,9 +487,16 @@ SDNode *AMDGPUDAGToDAGISel::Select(SDNode *N) {
case AMDGPUISD::DIV_SCALE: { case AMDGPUISD::DIV_SCALE: {
return SelectDIV_SCALE(N); return SelectDIV_SCALE(N);
} }
case ISD::CopyToReg: {
const SITargetLowering& Lowering =
*static_cast<const SITargetLowering*>(getTargetLowering());
Lowering.legalizeTargetIndependentNode(N, *CurDAG);
break;
}
case ISD::ADDRSPACECAST: case ISD::ADDRSPACECAST:
return SelectAddrSpaceCast(N); return SelectAddrSpaceCast(N);
} }
return SelectCode(N); return SelectCode(N);
} }

26
lib/Target/R600/SIISelLowering.cpp
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@@ -1920,28 +1920,26 @@ void SITargetLowering::adjustWritemask(MachineSDNode *&Node,
} }
} }
/// \brief Legalize INSERT_SUBREG instructions with frame index operands. /// \brief Legalize target independent instructions (e.g. INSERT_SUBREG)
/// LLVM assumes that all INSERT_SUBREG inputs are registers. /// with frame index operands.
static void legalizeInsertSubreg(MachineSDNode *InsertSubreg, /// LLVM assumes that inputs are to these instructions are registers.
SelectionDAG &DAG) { void SITargetLowering::legalizeTargetIndependentNode(SDNode *Node,
SelectionDAG &DAG) const {
assert(InsertSubreg->getMachineOpcode() == AMDGPU::INSERT_SUBREG);
SmallVector<SDValue, 8> Ops; SmallVector<SDValue, 8> Ops;
for (unsigned i = 0; i < 2; ++i) { for (unsigned i = 0; i < Node->getNumOperands(); ++i) {
if (!isa<FrameIndexSDNode>(InsertSubreg->getOperand(i))) { if (!isa<FrameIndexSDNode>(Node->getOperand(i))) {
Ops.push_back(InsertSubreg->getOperand(i)); Ops.push_back(Node->getOperand(i));
continue; continue;
} }
SDLoc DL(InsertSubreg); SDLoc DL(Node);
Ops.push_back(SDValue(DAG.getMachineNode(AMDGPU::S_MOV_B32, DL, Ops.push_back(SDValue(DAG.getMachineNode(AMDGPU::S_MOV_B32, DL,
InsertSubreg->getOperand(i).getValueType(), Node->getOperand(i).getValueType(),
InsertSubreg->getOperand(i)), 0)); Node->getOperand(i)), 0));
} }
DAG.UpdateNodeOperands(InsertSubreg, Ops[0], Ops[1], DAG.UpdateNodeOperands(Node, Ops);
InsertSubreg->getOperand(2));
} }
/// \brief Fold the instructions after selecting them. /// \brief Fold the instructions after selecting them.

1
lib/Target/R600/SIISelLowering.h
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@@ -101,6 +101,7 @@ public:
int32_t analyzeImmediate(const SDNode *N) const; int32_t analyzeImmediate(const SDNode *N) const;
SDValue CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC, SDValue CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC,
unsigned Reg, EVT VT) const override; unsigned Reg, EVT VT) const override;
void legalizeTargetIndependentNode(SDNode *Node, SelectionDAG &DAG) const;
}; };
} // End namespace llvm } // End namespace llvm

26
test/CodeGen/R600/copy-to-reg.ll Normal file
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@@ -0,0 +1,26 @@
; RUN: llc -march=r600 -mcpu=SI -mattr=-promote-alloca -verify-machineinstrs < %s
; Test that CopyToReg instructions don't have non-register operands prior
; to being emitted.
; Make sure this doesn't crash
; CHECK-LABEL: {{^}}copy_to_reg_frameindex:
define void @copy_to_reg_frameindex(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) {
entry:
%alloca = alloca [16 x i32]
br label %loop
loop:
%inc = phi i32 [0, %entry], [%inc.i, %loop]
%ptr = getelementptr [16 x i32]* %alloca, i32 0, i32 %inc
store i32 %inc, i32* %ptr
%inc.i = add i32 %inc, 1
%cnd = icmp uge i32 %inc.i, 16
br i1 %cnd, label %done, label %loop
done:
%tmp0 = getelementptr [16 x i32]* %alloca, i32 0, i32 0
%tmp1 = load i32* %tmp0
store i32 %tmp1, i32 addrspace(1)* %out
ret void
}