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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208922 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matt Arsenault 2014-05-15 21:44:05 +00:00
parent b043c3d94a
commit a8f7afaeb4
4 changed files with 45 additions and 62 deletions
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8
lib/Target/R600/AMDGPUISelLowering.cpp
View File

@ -222,10 +222,8 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
static const MVT::SimpleValueType IntTypes[] = {
MVT::v2i32, MVT::v4i32
};
const size_t NumIntTypes = array_lengthof(IntTypes);
for (unsigned int x = 0; x < NumIntTypes; ++x) {
MVT::SimpleValueType VT = IntTypes[x];
for (MVT VT : IntTypes) {
//Expand the following operations for the current type by default
setOperationAction(ISD::ADD, VT, Expand);
setOperationAction(ISD::AND, VT, Expand);
@ -249,10 +247,8 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
static const MVT::SimpleValueType FloatTypes[] = {
MVT::v2f32, MVT::v4f32
};
const size_t NumFloatTypes = array_lengthof(FloatTypes);
for (unsigned int x = 0; x < NumFloatTypes; ++x) {
MVT::SimpleValueType VT = FloatTypes[x];
for (MVT VT : FloatTypes) {
setOperationAction(ISD::FABS, VT, Expand);
setOperationAction(ISD::FADD, VT, Expand);
setOperationAction(ISD::FCOS, VT, Expand);

2
lib/Target/R600/AMDGPURegisterInfo.cpp
View File

@ -54,7 +54,7 @@ unsigned AMDGPURegisterInfo::getSubRegFromChannel(unsigned Channel) const {
AMDGPU::sub15
};
assert (Channel < array_lengthof(SubRegs));
assert(Channel < array_lengthof(SubRegs));
return SubRegs[Channel];
}

92
lib/Target/R600/AMDILISelLowering.cpp
View File

@ -39,61 +39,55 @@ using namespace llvm;
// TargetLowering Class Implementation Begins
//===----------------------------------------------------------------------===//
void AMDGPUTargetLowering::InitAMDILLowering() {
static const int types[] = {
(int)MVT::i8,
(int)MVT::i16,
(int)MVT::i32,
(int)MVT::f32,
(int)MVT::f64,
(int)MVT::i64,
(int)MVT::v2i8,
(int)MVT::v4i8,
(int)MVT::v2i16,
(int)MVT::v4i16,
(int)MVT::v4f32,
(int)MVT::v4i32,
(int)MVT::v2f32,
(int)MVT::v2i32,
(int)MVT::v2f64,
(int)MVT::v2i64
static const MVT::SimpleValueType types[] = {
MVT::i8,
MVT::i16,
MVT::i32,
MVT::f32,
MVT::f64,
MVT::i64,
MVT::v2i8,
MVT::v4i8,
MVT::v2i16,
MVT::v4i16,
MVT::v4f32,
MVT::v4i32,
MVT::v2f32,
MVT::v2i32,
MVT::v2f64,
MVT::v2i64
};
static const int IntTypes[] = {
(int)MVT::i8,
(int)MVT::i16,
(int)MVT::i32,
(int)MVT::i64
static const MVT::SimpleValueType IntTypes[] = {
MVT::i8,
MVT::i16,
MVT::i32,
MVT::i64
};
static const int FloatTypes[] = {
(int)MVT::f32,
(int)MVT::f64
static const MVT::SimpleValueType FloatTypes[] = {
MVT::f32,
MVT::f64
};
static const int VectorTypes[] = {
(int)MVT::v2i8,
(int)MVT::v4i8,
(int)MVT::v2i16,
(int)MVT::v4i16,
(int)MVT::v4f32,
(int)MVT::v4i32,
(int)MVT::v2f32,
(int)MVT::v2i32,
(int)MVT::v2f64,
(int)MVT::v2i64
static const MVT::SimpleValueType VectorTypes[] = {
MVT::v2i8,
MVT::v4i8,
MVT::v2i16,
MVT::v4i16,
MVT::v4f32,
MVT::v4i32,
MVT::v2f32,
MVT::v2i32,
MVT::v2f64,
MVT::v2i64
};
const size_t NumTypes = array_lengthof(types);
const size_t NumFloatTypes = array_lengthof(FloatTypes);
const size_t NumIntTypes = array_lengthof(IntTypes);
const size_t NumVectorTypes = array_lengthof(VectorTypes);
const AMDGPUSubtarget &STM = getTargetMachine().getSubtarget<AMDGPUSubtarget>();
// These are the current register classes that are
// supported
for (unsigned int x = 0; x < NumTypes; ++x) {
MVT::SimpleValueType VT = (MVT::SimpleValueType)types[x];
for (MVT VT : types) {
setOperationAction(ISD::SUBE, VT, Expand);
setOperationAction(ISD::SUBC, VT, Expand);
setOperationAction(ISD::ADDE, VT, Expand);
@ -109,9 +103,7 @@ void AMDGPUTargetLowering::InitAMDILLowering() {
setOperationAction(ISD::SDIV, VT, Custom);
}
}
for (unsigned int x = 0; x < NumFloatTypes; ++x) {
MVT::SimpleValueType VT = (MVT::SimpleValueType)FloatTypes[x];
for (MVT VT : FloatTypes) {
// IL does not have these operations for floating point types
setOperationAction(ISD::FP_ROUND_INREG, VT, Expand);
setOperationAction(ISD::SETOLT, VT, Expand);
@ -124,9 +116,7 @@ void AMDGPUTargetLowering::InitAMDILLowering() {
setOperationAction(ISD::SETULE, VT, Expand);
}
for (unsigned int x = 0; x < NumIntTypes; ++x) {
MVT::SimpleValueType VT = (MVT::SimpleValueType)IntTypes[x];
for (MVT VT : IntTypes) {
// GPU also does not have divrem function for signed or unsigned
setOperationAction(ISD::SDIVREM, VT, Expand);
@ -142,9 +132,7 @@ void AMDGPUTargetLowering::InitAMDILLowering() {
setOperationAction(ISD::CTLZ, VT, Expand);
}
for (unsigned int ii = 0; ii < NumVectorTypes; ++ii) {
MVT::SimpleValueType VT = (MVT::SimpleValueType)VectorTypes[ii];
for (MVT VT : VectorTypes) {
setOperationAction(ISD::VECTOR_SHUFFLE, VT, Expand);
setOperationAction(ISD::SDIVREM, VT, Expand);
setOperationAction(ISD::SMUL_LOHI, VT, Expand);

5
lib/Target/R600/SIISelLowering.cpp
View File

@ -179,8 +179,7 @@ SITargetLowering::SITargetLowering(TargetMachine &TM) :
MVT::v8i32, MVT::v8f32, MVT::v16i32, MVT::v16f32
};
const size_t NumVecTypes = array_lengthof(VecTypes);
for (unsigned Type = 0; Type < NumVecTypes; ++Type) {
for (MVT VT : VecTypes) {
for (unsigned Op = 0; Op < ISD::BUILTIN_OP_END; ++Op) {
switch(Op) {
case ISD::LOAD:
@ -194,7 +193,7 @@ SITargetLowering::SITargetLowering(TargetMachine &TM) :
case ISD::EXTRACT_SUBVECTOR:
break;
default:
setOperationAction(Op, VecTypes[Type], Expand);
setOperationAction(Op, VT, Expand);
break;
}
}