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Fix UnitTests/2005-05-13-SDivTwo.c
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21985 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -2675,7 +2675,6 @@ unsigned ISel::SelectExpr(SDOperand N) {
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}
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if (RHS && (RHS & (RHS-1)) == 0) { // Signed division by power of 2?
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unsigned Log = log2(RHS);
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unsigned TmpReg = MakeReg(N.getValueType());
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unsigned SAROpc, SHROpc, ADDOpc, NEGOpc;
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switch (N.getValueType()) {
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default: assert("Unknown type to signed divide!");
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@ -2698,10 +2697,12 @@ unsigned ISel::SelectExpr(SDOperand N) {
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NEGOpc = X86::NEG32r;
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break;
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}
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unsigned RegSize = MVT::getSizeInBits(N.getValueType());
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Tmp1 = SelectExpr(N.getOperand(0));
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unsigned TmpReg = MakeReg(N.getValueType());
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BuildMI(BB, SAROpc, 2, TmpReg).addReg(Tmp1).addImm(Log-1);
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unsigned TmpReg2 = MakeReg(N.getValueType());
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BuildMI(BB, SHROpc, 2, TmpReg2).addReg(TmpReg).addImm(32-Log);
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BuildMI(BB, SHROpc, 2, TmpReg2).addReg(TmpReg).addImm(RegSize-Log);
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unsigned TmpReg3 = MakeReg(N.getValueType());
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BuildMI(BB, ADDOpc, 2, TmpReg3).addReg(Tmp1).addReg(TmpReg2);
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@ -2924,7 +2924,7 @@ void X86ISel::emitDivRemOperation(MachineBasicBlock *BB,
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.addReg(Op0Reg).addImm(Log-1);
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unsigned TmpReg2 = makeAnotherReg(Op0->getType());
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BuildMI(*BB, IP, SHROpcode[Class], 2, TmpReg2)
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.addReg(TmpReg).addImm(32-Log);
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.addReg(TmpReg).addImm(CI->getType()->getPrimitiveSizeInBits()-Log);
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unsigned TmpReg3 = makeAnotherReg(Op0->getType());
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BuildMI(*BB, IP, ADDOpcode[Class], 2, TmpReg3)
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.addReg(Op0Reg).addReg(TmpReg2);
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