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Fix 80 column violations.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132341 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Richard Osborne 2011-05-31 16:30:33 +00:00
parent 9497466190
commit a9b08aa25e
2 changed files with 8 additions and 3 deletions
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4
include/llvm/IntrinsicsXCore.td
View File

@ -14,7 +14,9 @@ let TargetPrefix = "xcore" in { // All intrinsics start with "llvm.xcore.".
def int_xcore_crc8 : Intrinsic<[llvm_i32_ty, llvm_i32_ty],
[llvm_i32_ty,llvm_i32_ty,llvm_i32_ty],
[IntrNoMem]>;
def int_xcore_crc32 : Intrinsic<[llvm_i32_ty],[llvm_i32_ty,llvm_i32_ty,llvm_i32_ty],[IntrNoMem]>;
def int_xcore_crc32 : Intrinsic<[llvm_i32_ty],
[llvm_i32_ty,llvm_i32_ty,llvm_i32_ty],
[IntrNoMem]>;
def int_xcore_getid : Intrinsic<[llvm_i32_ty],[],[IntrNoMem]>;
def int_xcore_getps : Intrinsic<[llvm_i32_ty],[llvm_i32_ty]>;
def int_xcore_setps : Intrinsic<[],[llvm_i32_ty, llvm_i32_ty]>;

7
lib/Target/XCore/XCoreInstrInfo.td
View File

@ -474,9 +474,12 @@ def XOR_l3r : FL3R<"xor", xor>;
defm ASHR : FL3R_L2RBITP<"ashr", sra>;
let Constraints = "$src1 = $dst" in
def CRC_l3r : _FL3R<(outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
def CRC_l3r : _FL3R<(outs GRRegs:$dst),
(ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
"crc32 $dst, $src2, $src3",
[(set GRRegs:$dst, (int_xcore_crc32 GRRegs:$src1, GRRegs:$src2, GRRegs:$src3))]>;
[(set GRRegs:$dst,
(int_xcore_crc32 GRRegs:$src1, GRRegs:$src2,
GRRegs:$src3))]>;
// TODO inpw, outpw
let mayStore=1 in {