mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-01-28 21:34:23 +00:00
New "move to fp reg" routine. Use it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113537 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
ef2fdd2141
commit
aa3ace10c1
@ -131,6 +131,7 @@ class ARMFastISel : public FastISel {
|
|||||||
bool ARMComputeRegOffset(const Value *Obj, unsigned &Reg, int &Offset);
|
bool ARMComputeRegOffset(const Value *Obj, unsigned &Reg, int &Offset);
|
||||||
unsigned ARMMaterializeFP(const ConstantFP *CFP, EVT VT);
|
unsigned ARMMaterializeFP(const ConstantFP *CFP, EVT VT);
|
||||||
unsigned ARMMaterializeInt(const Constant *C);
|
unsigned ARMMaterializeInt(const Constant *C);
|
||||||
|
unsigned ARMMoveToFPReg(EVT VT, unsigned SrcReg);
|
||||||
|
|
||||||
bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR);
|
bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR);
|
||||||
const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB);
|
const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB);
|
||||||
@ -330,6 +331,16 @@ unsigned ARMFastISel::FastEmitInst_extractsubreg(MVT RetVT,
|
|||||||
return ResultReg;
|
return ResultReg;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
unsigned ARMFastISel::ARMMoveToFPReg(EVT VT, unsigned SrcReg) {
|
||||||
|
// If we have a floating point constant we expect it in a floating point
|
||||||
|
// register.
|
||||||
|
unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
|
||||||
|
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
|
||||||
|
TII.get(ARM::VMOVRS), MoveReg)
|
||||||
|
.addReg(SrcReg));
|
||||||
|
return MoveReg;
|
||||||
|
}
|
||||||
|
|
||||||
// For double width floating point we need to materialize two constants
|
// For double width floating point we need to materialize two constants
|
||||||
// (the high and the low) into integer registers then use a move to get
|
// (the high and the low) into integer registers then use a move to get
|
||||||
// the combined constant into an FP reg.
|
// the combined constant into an FP reg.
|
||||||
@ -356,11 +367,7 @@ unsigned ARMFastISel::ARMMaterializeFP(const ConstantFP *CFP, EVT VT) {
|
|||||||
|
|
||||||
// If we have a floating point constant we expect it in a floating point
|
// If we have a floating point constant we expect it in a floating point
|
||||||
// register.
|
// register.
|
||||||
unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT));
|
return ARMMoveToFPReg(VT, DestReg);
|
||||||
AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
|
|
||||||
TII.get(ARM::VMOVRS), MoveReg)
|
|
||||||
.addReg(DestReg));
|
|
||||||
return MoveReg;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
unsigned ARMFastISel::ARMMaterializeInt(const Constant *C) {
|
unsigned ARMFastISel::ARMMaterializeInt(const Constant *C) {
|
||||||
|
Loading…
x
Reference in New Issue
Block a user