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Expose move to/from coprocessor instructions in MIPS64 mode.

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Note: [D]M{T,F}CP2 is just a recommended encoding.  Vendors often provide a
custom CP2 that interprets instructions differently and may wish to add their
own instructions that use this opcode.  We should ensure that this is easy to
do.  I will probably add a 'has custom CP{0-3}' subtarget flag to make this
easy: We want to avoid the GCC situation where every MIPS vendor makes a custom
fork that breaks every other MIPS CPU and so can't be merged upstream.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165711 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
David Chisnall 2012-10-11 10:21:34 +00:00
parent 54d2d2bbe9
commit aa5b393c69
2 changed files with 67 additions and 0 deletions
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30
lib/Target/Mips/Mips64InstrInfo.td
View File

@ -315,3 +315,33 @@ def : MipsPat<(bswap CPU64Regs:$rt), (DSHD (DSBH CPU64Regs:$rt))>;
// Instruction aliases
//===----------------------------------------------------------------------===//
def : InstAlias<"move $dst,$src", (DADD CPU64Regs:$dst,CPU64Regs:$src,ZERO_64)>;
/// Move between CPU and coprocessor registers
let DecoderNamespace = "Mips64" in {
def MFC0_3OP64 : MFC3OP<0x10, 0, (outs CPU64Regs:$rt),
(ins CPU64Regs:$rd, uimm16:$sel),"mfc0\t$rt, $rd, $sel">;
def MTC0_3OP64 : MFC3OP<0x10, 4, (outs CPU64Regs:$rd, uimm16:$sel),
(ins CPU64Regs:$rt),"mtc0\t$rt, $rd, $sel">;
def MFC2_3OP64 : MFC3OP<0x12, 0, (outs CPU64Regs:$rt),
(ins CPU64Regs:$rd, uimm16:$sel),"mfc2\t$rt, $rd, $sel">;
def MTC2_3OP64 : MFC3OP<0x12, 4, (outs CPU64Regs:$rd, uimm16:$sel),
(ins CPU64Regs:$rt),"mtc2\t$rt, $rd, $sel">;
def DMFC0_3OP64 : MFC3OP<0x10, 1, (outs CPU64Regs:$rt),
(ins CPU64Regs:$rd, uimm16:$sel),"dmfc0\t$rt, $rd, $sel">;
def DMTC0_3OP64 : MFC3OP<0x10, 5, (outs CPU64Regs:$rd, uimm16:$sel),
(ins CPU64Regs:$rt),"dmtc0\t$rt, $rd, $sel">;
def DMFC2_3OP64 : MFC3OP<0x12, 1, (outs CPU64Regs:$rt),
(ins CPU64Regs:$rd, uimm16:$sel),"dmfc2\t$rt, $rd, $sel">;
def DMTC2_3OP64 : MFC3OP<0x12, 5, (outs CPU64Regs:$rd, uimm16:$sel),
(ins CPU64Regs:$rt),"dmtc2\t$rt, $rd, $sel">;
}
// Two operand (implicit 0 selector) versions:
def : InstAlias<"mfc0 $rt, $rd", (MFC0_3OP64 CPU64Regs:$rt, CPU64Regs:$rd, 0)>;
def : InstAlias<"mtc0 $rt, $rd", (MTC0_3OP64 CPU64Regs:$rd, 0, CPU64Regs:$rt)>;
def : InstAlias<"mfc2 $rt, $rd", (MFC2_3OP64 CPU64Regs:$rt, CPU64Regs:$rd, 0)>;
def : InstAlias<"mtc2 $rt, $rd", (MTC2_3OP64 CPU64Regs:$rd, 0, CPU64Regs:$rt)>;
def : InstAlias<"dmfc0 $rt, $rd", (DMFC0_3OP64 CPU64Regs:$rt, CPU64Regs:$rd, 0)>;
def : InstAlias<"dmtc0 $rt, $rd", (DMTC0_3OP64 CPU64Regs:$rd, 0, CPU64Regs:$rt)>;
def : InstAlias<"dmfc2 $rt, $rd", (DMFC2_3OP64 CPU64Regs:$rt, CPU64Regs:$rd, 0)>;
def : InstAlias<"dmtc2 $rt, $rd", (DMTC2_3OP64 CPU64Regs:$rd, 0, CPU64Regs:$rt)>;

37
test/MC/Mips/mips-coprocessor-encodings.s Normal file
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@ -0,0 +1,37 @@
# RUN: llvm-mc %s -triple=mips64-unknown-freebsd -show-encoding | FileCheck --check-prefix=MIPS64 %s
# MIPS64: dmtc0 $12, $16, 2 # encoding: [0x40,0xac,0x80,0x02]
# MIPS64: dmtc0 $12, $16, 0 # encoding: [0x40,0xac,0x80,0x00]
# MIPS64: mtc0 $12, $16, 2 # encoding: [0x40,0x8c,0x80,0x02]
# MIPS64: mtc0 $12, $16, 0 # encoding: [0x40,0x8c,0x80,0x00]
# MIPS64: dmfc0 $12, $16, 2 # encoding: [0x40,0x2c,0x80,0x02]
# MIPS64: dmfc0 $12, $16, 0 # encoding: [0x40,0x2c,0x80,0x00]
# MIPS64: mfc0 $12, $16, 2 # encoding: [0x40,0x0c,0x80,0x02]
# MIPS64: mfc0 $12, $16, 0 # encoding: [0x40,0x0c,0x80,0x00]
dmtc0 $12, $16, 2
dmtc0 $12, $16
mtc0 $12, $16, 2
mtc0 $12, $16
dmfc0 $12, $16, 2
dmfc0 $12, $16
mfc0 $12, $16, 2
mfc0 $12, $16
# MIPS64: dmtc2 $12, $16, 2 # encoding: [0x48,0xac,0x80,0x02]
# MIPS64: dmtc2 $12, $16, 0 # encoding: [0x48,0xac,0x80,0x00]
# MIPS64: mtc2 $12, $16, 2 # encoding: [0x48,0x8c,0x80,0x02]
# MIPS64: mtc2 $12, $16, 0 # encoding: [0x48,0x8c,0x80,0x00]
# MIPS64: dmfc2 $12, $16, 2 # encoding: [0x48,0x2c,0x80,0x02]
# MIPS64: dmfc2 $12, $16, 0 # encoding: [0x48,0x2c,0x80,0x00]
# MIPS64: mfc2 $12, $16, 2 # encoding: [0x48,0x0c,0x80,0x02]
# MIPS64: mfc2 $12, $16, 0 # encoding: [0x48,0x0c,0x80,0x00]
dmtc2 $12, $16, 2
dmtc2 $12, $16
mtc2 $12, $16, 2
mtc2 $12, $16
dmfc2 $12, $16, 2
dmfc2 $12, $16
mfc2 $12, $16, 2
mfc2 $12, $16