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PPC: Use HWEncoding and TRI->getEncodingValue

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As pointed out by Jakob, we don't need to maintain a separate
register-numbering table. Instead we should let TableGen generate the table for
us from the information (already present) in PPCRegisterInfo.td.
TRI->getEncodingValue is now used to access register-encoding values.

No functionality change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178067 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Hal Finkel
2013-03-26 20:08:20 +00:00
parent 4d419bffb7
commit aa6047d23d
8 changed files with 31 additions and 100 deletions
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4
lib/Target/PowerPC/PPCRegisterInfo.cpp
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@@ -328,7 +328,7 @@ void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II,
// rlwinm rA, rA, ShiftBits, 0, 31.
BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
.addReg(Reg1, RegState::Kill)
.addImm(getPPCRegisterNumbering(SrcReg) * 4)
.addImm(getEncodingValue(SrcReg) * 4)
.addImm(0)
.addImm(31);
}
@@ -368,7 +368,7 @@ void PPCRegisterInfo::lowerCRRestore(MachineBasicBlock::iterator II,
unsigned Reg1 = Reg;
Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC);
unsigned ShiftBits = getPPCRegisterNumbering(DestReg)*4;
unsigned ShiftBits = getEncodingValue(DestReg)*4;
// rlwinm r11, r11, 32-ShiftBits, 0, 31.
BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
.addReg(Reg1, RegState::Kill).addImm(32-ShiftBits).addImm(0)