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R600/SI: Implement spilling of SGPRs v5
SGPRs are spilled into VGPRs using the {READ,WRITE}LANE_B32 instructions. v2: - Fix encoding of Lane Mask - Use correct register flags, so we don't overwrite the low dword when restoring multi-dword registers. v3: - Register spilling seems to hang the GPU, so replace all shaders that need spilling with a dummy shader. v4: - Fix *LANE definitions - Change destination reg class for 32-bit SMRD instructions v5: - Remove small optimization that was crashing Serious Sam 3. https://bugs.freedesktop.org/show_bug.cgi?id=68224 https://bugs.freedesktop.org/show_bug.cgi?id=71285 NOTE: This is a candidate for the 3.4 branch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195880 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -10,6 +10,10 @@
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#include "SIMachineFunctionInfo.h"
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#include "SIRegisterInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#define MAX_LANES 64
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using namespace llvm;
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@ -19,4 +23,33 @@ void SIMachineFunctionInfo::anchor() {}
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SIMachineFunctionInfo::SIMachineFunctionInfo(const MachineFunction &MF)
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: AMDGPUMachineFunction(MF),
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PSInputAddr(0) { }
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PSInputAddr(0),
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SpillTracker() { }
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static unsigned createLaneVGPR(MachineRegisterInfo &MRI) {
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return MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
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}
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unsigned SIMachineFunctionInfo::RegSpillTracker::getNextLane(MachineRegisterInfo &MRI) {
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if (!LaneVGPR) {
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LaneVGPR = createLaneVGPR(MRI);
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} else {
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CurrentLane++;
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if (CurrentLane == MAX_LANES) {
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CurrentLane = 0;
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LaneVGPR = createLaneVGPR(MRI);
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}
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}
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return CurrentLane;
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}
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void SIMachineFunctionInfo::RegSpillTracker::addSpilledReg(unsigned FrameIndex,
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unsigned Reg,
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int Lane) {
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SpilledRegisters[FrameIndex] = SpilledReg(Reg, Lane);
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}
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const SIMachineFunctionInfo::SpilledReg&
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SIMachineFunctionInfo::RegSpillTracker::getSpilledReg(unsigned FrameIndex) {
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return SpilledRegisters[FrameIndex];
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}
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