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[C++11] Add 'override' keywords and remove 'virtual'. Additionally add 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. Hexagon edition

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207508 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper 2014-04-29 07:58:16 +00:00
parent e17a0260a8
commit aab65f8023
22 changed files with 188 additions and 189 deletions
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11
lib/Target/Hexagon/HexagonAsmPrinter.h
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@ -30,21 +30,22 @@ namespace llvm {
Subtarget = &TM.getSubtarget<HexagonSubtarget>(); Subtarget = &TM.getSubtarget<HexagonSubtarget>();
} }
virtual const char *getPassName() const { const char *getPassName() const override {
return "Hexagon Assembly Printer"; return "Hexagon Assembly Printer";
} }
bool isBlockOnlyReachableByFallthrough(const MachineBasicBlock *MBB) const; bool isBlockOnlyReachableByFallthrough(
const MachineBasicBlock *MBB) const override;
virtual void EmitInstruction(const MachineInstr *MI); void EmitInstruction(const MachineInstr *MI) override;
void printOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O); void printOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O);
bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
unsigned AsmVariant, const char *ExtraCode, unsigned AsmVariant, const char *ExtraCode,
raw_ostream &OS); raw_ostream &OS) override;
bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo, bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
unsigned AsmVariant, const char *ExtraCode, unsigned AsmVariant, const char *ExtraCode,
raw_ostream &OS); raw_ostream &OS) override;
static const char *getRegisterName(unsigned RegNo); static const char *getRegisterName(unsigned RegNo);
}; };

4
lib/Target/Hexagon/HexagonCFGOptimizer.cpp
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@ -49,10 +49,10 @@ private:
initializeHexagonCFGOptimizerPass(*PassRegistry::getPassRegistry()); initializeHexagonCFGOptimizerPass(*PassRegistry::getPassRegistry());
} }
const char *getPassName() const { const char *getPassName() const override {
return "Hexagon CFG Optimizer"; return "Hexagon CFG Optimizer";
} }
bool runOnMachineFunction(MachineFunction &Fn); bool runOnMachineFunction(MachineFunction &Fn) override;
}; };

6
lib/Target/Hexagon/HexagonCopyToCombine.cpp
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@ -68,15 +68,15 @@ public:
initializeHexagonCopyToCombinePass(*PassRegistry::getPassRegistry()); initializeHexagonCopyToCombinePass(*PassRegistry::getPassRegistry());
} }
virtual void getAnalysisUsage(AnalysisUsage &AU) const { void getAnalysisUsage(AnalysisUsage &AU) const override {
MachineFunctionPass::getAnalysisUsage(AU); MachineFunctionPass::getAnalysisUsage(AU);
} }
const char *getPassName() const { const char *getPassName() const override {
return "Hexagon Copy-To-Combine Pass"; return "Hexagon Copy-To-Combine Pass";
} }
virtual bool runOnMachineFunction(MachineFunction &Fn); bool runOnMachineFunction(MachineFunction &Fn) override;
private: private:
MachineInstr *findPairable(MachineInstr *I1, bool &DoInsertAtI1); MachineInstr *findPairable(MachineInstr *I1, bool &DoInsertAtI1);

4
lib/Target/Hexagon/HexagonExpandPredSpillCode.cpp
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@ -60,10 +60,10 @@ class HexagonExpandPredSpillCode : public MachineFunctionPass {
initializeHexagonExpandPredSpillCodePass(Registry); initializeHexagonExpandPredSpillCodePass(Registry);
} }
const char *getPassName() const { const char *getPassName() const override {
return "Hexagon Expand Predicate Spill Code"; return "Hexagon Expand Predicate Spill Code";
} }
bool runOnMachineFunction(MachineFunction &Fn); bool runOnMachineFunction(MachineFunction &Fn) override;
}; };

8
lib/Target/Hexagon/HexagonFixupHwLoops.cpp
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@ -40,11 +40,13 @@ namespace {
initializeHexagonFixupHwLoopsPass(*PassRegistry::getPassRegistry()); initializeHexagonFixupHwLoopsPass(*PassRegistry::getPassRegistry());
} }
virtual bool runOnMachineFunction(MachineFunction &MF); bool runOnMachineFunction(MachineFunction &MF) override;
const char *getPassName() const { return "Hexagon Hardware Loop Fixup"; } const char *getPassName() const override {
return "Hexagon Hardware Loop Fixup";
}
virtual void getAnalysisUsage(AnalysisUsage &AU) const { void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.setPreservesCFG(); AU.setPreservesCFG();
MachineFunctionPass::getAnalysisUsage(AU); MachineFunctionPass::getAnalysisUsage(AU);
} }

28
lib/Target/Hexagon/HexagonFrameLowering.h
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@ -28,25 +28,25 @@ public:
/// emitProlog/emitEpilog - These methods insert prolog and epilog code into /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
/// the function. /// the function.
void emitPrologue(MachineFunction &MF) const; void emitPrologue(MachineFunction &MF) const override;
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const; void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
virtual bool bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
spillCalleeSavedRegisters(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
MachineBasicBlock::iterator MI, const std::vector<CalleeSavedInfo> &CSI,
const std::vector<CalleeSavedInfo> &CSI, const TargetRegisterInfo *TRI) const override;
const TargetRegisterInfo *TRI) const;
void eliminateCallFramePseudoInstr(MachineFunction &MF, void
MachineBasicBlock &MBB, eliminateCallFramePseudoInstr(MachineFunction &MF,
MachineBasicBlock::iterator I) const; MachineBasicBlock &MBB,
MachineBasicBlock::iterator I) const override;
virtual bool bool
restoreCalleeSavedRegisters(MachineBasicBlock &MBB, restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI, MachineBasicBlock::iterator MI,
const std::vector<CalleeSavedInfo> &CSI, const std::vector<CalleeSavedInfo> &CSI,
const TargetRegisterInfo *TRI) const; const TargetRegisterInfo *TRI) const override;
int getFrameIndexOffset(const MachineFunction &MF, int FI) const; int getFrameIndexOffset(const MachineFunction &MF, int FI) const override;
bool hasFP(const MachineFunction &MF) const; bool hasFP(const MachineFunction &MF) const override;
bool hasTailCall(MachineBasicBlock &MBB) const; bool hasTailCall(MachineBasicBlock &MBB) const;
}; };

6
lib/Target/Hexagon/HexagonHardwareLoops.cpp
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@ -78,11 +78,11 @@ namespace {
initializeHexagonHardwareLoopsPass(*PassRegistry::getPassRegistry()); initializeHexagonHardwareLoopsPass(*PassRegistry::getPassRegistry());
} }
virtual bool runOnMachineFunction(MachineFunction &MF); bool runOnMachineFunction(MachineFunction &MF) override;
const char *getPassName() const { return "Hexagon Hardware Loops"; } const char *getPassName() const override { return "Hexagon Hardware Loops"; }
virtual void getAnalysisUsage(AnalysisUsage &AU) const { void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.addRequired<MachineDominatorTree>(); AU.addRequired<MachineDominatorTree>();
AU.addRequired<MachineLoopInfo>(); AU.addRequired<MachineLoopInfo>();
MachineFunctionPass::getAnalysisUsage(AU); MachineFunctionPass::getAnalysisUsage(AU);

10
lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
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@ -62,7 +62,7 @@ public:
} }
bool hasNumUsesBelowThresGA(SDNode *N) const; bool hasNumUsesBelowThresGA(SDNode *N) const;
SDNode *Select(SDNode *N); SDNode *Select(SDNode *N) override;
// Complex Pattern Selectors. // Complex Pattern Selectors.
inline bool foldGlobalAddress(SDValue &N, SDValue &R); inline bool foldGlobalAddress(SDValue &N, SDValue &R);
@ -79,15 +79,15 @@ public:
bool SelectADDRriU6_1(SDValue& N, SDValue &R1, SDValue &R2); bool SelectADDRriU6_1(SDValue& N, SDValue &R1, SDValue &R2);
bool SelectADDRriU6_2(SDValue& N, SDValue &R1, SDValue &R2); bool SelectADDRriU6_2(SDValue& N, SDValue &R1, SDValue &R2);
virtual const char *getPassName() const { const char *getPassName() const override {
return "Hexagon DAG->DAG Pattern Instruction Selection"; return "Hexagon DAG->DAG Pattern Instruction Selection";
} }
/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
/// inline asm expressions. /// inline asm expressions.
virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op, bool SelectInlineAsmMemoryOperand(const SDValue &Op,
char ConstraintCode, char ConstraintCode,
std::vector<SDValue> &OutOps); std::vector<SDValue> &OutOps) override;
bool SelectAddr(SDNode *Op, SDValue Addr, SDValue &Base, SDValue &Offset); bool SelectAddr(SDNode *Op, SDValue Addr, SDValue &Base, SDValue &Offset);
SDNode *SelectLoad(SDNode *N); SDNode *SelectLoad(SDNode *N);

43
lib/Target/Hexagon/HexagonISelLowering.h
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@ -92,14 +92,14 @@ namespace llvm {
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
SelectionDAG& DAG) const; SelectionDAG& DAG) const;
virtual bool isTruncateFree(Type *Ty1, Type *Ty2) const; bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
virtual bool isTruncateFree(EVT VT1, EVT VT2) const; bool isTruncateFree(EVT VT1, EVT VT2) const override;
virtual bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const; bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const; SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
virtual const char *getTargetNodeName(unsigned Opcode) const; const char *getTargetNodeName(unsigned Opcode) const override;
SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const; SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const; SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const; SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const;
@ -109,12 +109,12 @@ namespace llvm {
CallingConv::ID CallConv, bool isVarArg, CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,
SDLoc dl, SelectionDAG &DAG, SDLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) const; SmallVectorImpl<SDValue> &InVals) const override;
SDValue LowerGLOBALADDRESS(SDValue Op, SelectionDAG &DAG) const; SDValue LowerGLOBALADDRESS(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const; SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI, SDValue LowerCall(TargetLowering::CallLoweringInfo &CLI,
SmallVectorImpl<SDValue> &InVals) const; SmallVectorImpl<SDValue> &InVals) const override;
SDValue LowerCallResult(SDValue Chain, SDValue InFlag, SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
CallingConv::ID CallConv, bool isVarArg, CallingConv::ID CallConv, bool isVarArg,
@ -133,46 +133,45 @@ namespace llvm {
CallingConv::ID CallConv, bool isVarArg, CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<SDValue> &OutVals, const SmallVectorImpl<SDValue> &OutVals,
SDLoc dl, SelectionDAG &DAG) const; SDLoc dl, SelectionDAG &DAG) const override;
virtual MachineBasicBlock MachineBasicBlock *
*EmitInstrWithCustomInserter(MachineInstr *MI, EmitInstrWithCustomInserter(MachineInstr *MI,
MachineBasicBlock *BB) const; MachineBasicBlock *BB) const override;
SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const; SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const; SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
virtual EVT getSetCCResultType(LLVMContext &C, EVT VT) const { EVT getSetCCResultType(LLVMContext &C, EVT VT) const override {
if (!VT.isVector()) if (!VT.isVector())
return MVT::i1; return MVT::i1;
else else
return EVT::getVectorVT(C, MVT::i1, VT.getVectorNumElements()); return EVT::getVectorVT(C, MVT::i1, VT.getVectorNumElements());
} }
virtual bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, bool getPostIndexedAddressParts(SDNode *N, SDNode *Op,
SDValue &Base, SDValue &Offset, SDValue &Base, SDValue &Offset,
ISD::MemIndexedMode &AM, ISD::MemIndexedMode &AM,
SelectionDAG &DAG) const; SelectionDAG &DAG) const override;
std::pair<unsigned, const TargetRegisterClass*> std::pair<unsigned, const TargetRegisterClass*>
getRegForInlineAsmConstraint(const std::string &Constraint, getRegForInlineAsmConstraint(const std::string &Constraint,
MVT VT) const; MVT VT) const override;
// Intrinsics // Intrinsics
virtual SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
SelectionDAG &DAG) const;
/// isLegalAddressingMode - Return true if the addressing mode represented /// isLegalAddressingMode - Return true if the addressing mode represented
/// by AM is legal for this target, for a load/store of the specified type. /// by AM is legal for this target, for a load/store of the specified type.
/// The type may be VoidTy, in which case only return true if the addressing /// The type may be VoidTy, in which case only return true if the addressing
/// mode is legal for a load/store of any legal type. /// mode is legal for a load/store of any legal type.
/// TODO: Handle pre/postinc as well. /// TODO: Handle pre/postinc as well.
virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const; bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override;
virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const; bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
/// isLegalICmpImmediate - Return true if the specified immediate is legal /// isLegalICmpImmediate - Return true if the specified immediate is legal
/// icmp immediate, that is the target has icmp instructions which can /// icmp immediate, that is the target has icmp instructions which can
/// compare a register against the immediate without having to materialize /// compare a register against the immediate without having to materialize
/// the immediate into a register. /// the immediate into a register.
virtual bool isLegalICmpImmediate(int64_t Imm) const; bool isLegalICmpImmediate(int64_t Imm) const override;
}; };
} // end namespace llvm } // end namespace llvm

159
lib/Target/Hexagon/HexagonInstrInfo.h
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@ -40,124 +40,121 @@ public:
/// such, whenever a client has an instance of instruction info, it should /// such, whenever a client has an instance of instruction info, it should
/// always be able to get register info as well (through this method). /// always be able to get register info as well (through this method).
/// ///
virtual const HexagonRegisterInfo &getRegisterInfo() const { return RI; } const HexagonRegisterInfo &getRegisterInfo() const { return RI; }
/// isLoadFromStackSlot - If the specified machine instruction is a direct /// isLoadFromStackSlot - If the specified machine instruction is a direct
/// load from a stack slot, return the virtual or physical register number of /// load from a stack slot, return the virtual or physical register number of
/// the destination along with the FrameIndex of the loaded stack slot. If /// the destination along with the FrameIndex of the loaded stack slot. If
/// not, return 0. This predicate must return 0 if the instruction has /// not, return 0. This predicate must return 0 if the instruction has
/// any side effects other than loading from the stack slot. /// any side effects other than loading from the stack slot.
virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, unsigned isLoadFromStackSlot(const MachineInstr *MI,
int &FrameIndex) const; int &FrameIndex) const override;
/// isStoreToStackSlot - If the specified machine instruction is a direct /// isStoreToStackSlot - If the specified machine instruction is a direct
/// store to a stack slot, return the virtual or physical register number of /// store to a stack slot, return the virtual or physical register number of
/// the source reg along with the FrameIndex of the loaded stack slot. If /// the source reg along with the FrameIndex of the loaded stack slot. If
/// not, return 0. This predicate must return 0 if the instruction has /// not, return 0. This predicate must return 0 if the instruction has
/// any side effects other than storing to the stack slot. /// any side effects other than storing to the stack slot.
virtual unsigned isStoreToStackSlot(const MachineInstr *MI, unsigned isStoreToStackSlot(const MachineInstr *MI,
int &FrameIndex) const; int &FrameIndex) const override;
virtual bool AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, bool AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
MachineBasicBlock *&FBB, MachineBasicBlock *&FBB,
SmallVectorImpl<MachineOperand> &Cond, SmallVectorImpl<MachineOperand> &Cond,
bool AllowModify) const; bool AllowModify) const override;
virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB, MachineBasicBlock *FBB,
const SmallVectorImpl<MachineOperand> &Cond, const SmallVectorImpl<MachineOperand> &Cond,
DebugLoc DL) const; DebugLoc DL) const override;
virtual bool analyzeCompare(const MachineInstr *MI, bool analyzeCompare(const MachineInstr *MI,
unsigned &SrcReg, unsigned &SrcReg2, unsigned &SrcReg, unsigned &SrcReg2,
int &Mask, int &Value) const; int &Mask, int &Value) const override;
virtual void copyPhysReg(MachineBasicBlock &MBB, void copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I, DebugLoc DL, MachineBasicBlock::iterator I, DebugLoc DL,
unsigned DestReg, unsigned SrcReg, unsigned DestReg, unsigned SrcReg,
bool KillSrc) const; bool KillSrc) const override;
virtual void storeRegToStackSlot(MachineBasicBlock &MBB, void storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI, MachineBasicBlock::iterator MBBI,
unsigned SrcReg, bool isKill, int FrameIndex, unsigned SrcReg, bool isKill, int FrameIndex,
const TargetRegisterClass *RC, const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI) const; const TargetRegisterInfo *TRI) const override;
virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill, void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
SmallVectorImpl<MachineOperand> &Addr, SmallVectorImpl<MachineOperand> &Addr,
const TargetRegisterClass *RC, const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const; SmallVectorImpl<MachineInstr*> &NewMIs) const;
virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, void loadRegFromStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI, MachineBasicBlock::iterator MBBI,
unsigned DestReg, int FrameIndex, unsigned DestReg, int FrameIndex,
const TargetRegisterClass *RC, const TargetRegisterClass *RC,
const TargetRegisterInfo *TRI) const; const TargetRegisterInfo *TRI) const override;
virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg, void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
SmallVectorImpl<MachineOperand> &Addr, SmallVectorImpl<MachineOperand> &Addr,
const TargetRegisterClass *RC, const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const; SmallVectorImpl<MachineInstr*> &NewMIs) const;
virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
MachineInstr* MI, MachineInstr* MI,
const SmallVectorImpl<unsigned> &Ops, const SmallVectorImpl<unsigned> &Ops,
int FrameIndex) const; int FrameIndex) const override;
virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF, MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
MachineInstr* MI, MachineInstr* MI,
const SmallVectorImpl<unsigned> &Ops, const SmallVectorImpl<unsigned> &Ops,
MachineInstr* LoadMI) const { MachineInstr* LoadMI) const override {
return nullptr; return nullptr;
} }
unsigned createVR(MachineFunction* MF, MVT VT) const; unsigned createVR(MachineFunction* MF, MVT VT) const;
virtual bool isBranch(const MachineInstr *MI) const; bool isBranch(const MachineInstr *MI) const;
virtual bool isPredicable(MachineInstr *MI) const; bool isPredicable(MachineInstr *MI) const override;
virtual bool bool PredicateInstruction(MachineInstr *MI,
PredicateInstruction(MachineInstr *MI, const SmallVectorImpl<MachineOperand> &Cond) const override;
const SmallVectorImpl<MachineOperand> &Cond) const;
virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
unsigned ExtraPredCycles, unsigned ExtraPredCycles,
const BranchProbability &Probability) const; const BranchProbability &Probability) const override;
virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB, bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
unsigned NumTCycles, unsigned ExtraTCycles, unsigned NumTCycles, unsigned ExtraTCycles,
MachineBasicBlock &FMBB, MachineBasicBlock &FMBB,
unsigned NumFCycles, unsigned ExtraFCycles, unsigned NumFCycles, unsigned ExtraFCycles,
const BranchProbability &Probability) const; const BranchProbability &Probability) const override;
virtual bool isPredicated(const MachineInstr *MI) const; bool isPredicated(const MachineInstr *MI) const override;
virtual bool isPredicated(unsigned Opcode) const; bool isPredicated(unsigned Opcode) const;
virtual bool isPredicatedTrue(const MachineInstr *MI) const; bool isPredicatedTrue(const MachineInstr *MI) const;
virtual bool isPredicatedTrue(unsigned Opcode) const; bool isPredicatedTrue(unsigned Opcode) const;
virtual bool isPredicatedNew(const MachineInstr *MI) const; bool isPredicatedNew(const MachineInstr *MI) const;
virtual bool isPredicatedNew(unsigned Opcode) const; bool isPredicatedNew(unsigned Opcode) const;
virtual bool DefinesPredicate(MachineInstr *MI, bool DefinesPredicate(MachineInstr *MI,
std::vector<MachineOperand> &Pred) const; std::vector<MachineOperand> &Pred) const override;
virtual bool bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1, const SmallVectorImpl<MachineOperand> &Pred2) const override;
const SmallVectorImpl<MachineOperand> &Pred2) const;
virtual bool bool
ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const; ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
virtual bool bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
isProfitableToDupForIfCvt(MachineBasicBlock &MBB,unsigned NumCycles, const BranchProbability &Probability) const override;
const BranchProbability &Probability) const;
virtual DFAPacketizer* DFAPacketizer*
CreateTargetScheduleState(const TargetMachine *TM, CreateTargetScheduleState(const TargetMachine *TM,
const ScheduleDAG *DAG) const; const ScheduleDAG *DAG) const override;
virtual bool isSchedulingBoundary(const MachineInstr *MI, bool isSchedulingBoundary(const MachineInstr *MI,
const MachineBasicBlock *MBB, const MachineBasicBlock *MBB,
const MachineFunction &MF) const; const MachineFunction &MF) const override;
bool isValidOffset(const int Opcode, const int Offset) const; bool isValidOffset(const int Opcode, const int Offset) const;
bool isValidAutoIncImm(const EVT VT, const int Offset) const; bool isValidAutoIncImm(const EVT VT, const int Offset) const;
bool isMemOp(const MachineInstr *MI) const; bool isMemOp(const MachineInstr *MI) const;

6
lib/Target/Hexagon/HexagonNewValueJump.cpp
View File

@ -75,16 +75,16 @@ namespace {
initializeHexagonNewValueJumpPass(*PassRegistry::getPassRegistry()); initializeHexagonNewValueJumpPass(*PassRegistry::getPassRegistry());
} }
virtual void getAnalysisUsage(AnalysisUsage &AU) const { void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.addRequired<MachineBranchProbabilityInfo>(); AU.addRequired<MachineBranchProbabilityInfo>();
MachineFunctionPass::getAnalysisUsage(AU); MachineFunctionPass::getAnalysisUsage(AU);
} }
const char *getPassName() const { const char *getPassName() const override {
return "Hexagon NewValueJump"; return "Hexagon NewValueJump";
} }
virtual bool runOnMachineFunction(MachineFunction &Fn); bool runOnMachineFunction(MachineFunction &Fn) override;
private: private:
/// \brief A handle to the branch probability pass. /// \brief A handle to the branch probability pass.

6
lib/Target/Hexagon/HexagonPeephole.cpp
View File

@ -90,13 +90,13 @@ namespace {
initializeHexagonPeepholePass(*PassRegistry::getPassRegistry()); initializeHexagonPeepholePass(*PassRegistry::getPassRegistry());
} }
bool runOnMachineFunction(MachineFunction &MF); bool runOnMachineFunction(MachineFunction &MF) override;
const char *getPassName() const { const char *getPassName() const override {
return "Hexagon optimize redundant zero and size extends"; return "Hexagon optimize redundant zero and size extends";
} }
void getAnalysisUsage(AnalysisUsage &AU) const { void getAnalysisUsage(AnalysisUsage &AU) const override {
MachineFunctionPass::getAnalysisUsage(AU); MachineFunctionPass::getAnalysisUsage(AU);
} }

12
lib/Target/Hexagon/HexagonRegisterInfo.h
View File

@ -49,16 +49,16 @@ struct HexagonRegisterInfo : public HexagonGenRegisterInfo {
/// Code Generation virtual methods... /// Code Generation virtual methods...
const MCPhysReg * const MCPhysReg *
getCalleeSavedRegs(const MachineFunction *MF = nullptr) const; getCalleeSavedRegs(const MachineFunction *MF = nullptr) const override;
const TargetRegisterClass* const* const TargetRegisterClass* const*
getCalleeSavedRegClasses(const MachineFunction *MF = nullptr) const; getCalleeSavedRegClasses(const MachineFunction *MF = nullptr) const;
BitVector getReservedRegs(const MachineFunction &MF) const; BitVector getReservedRegs(const MachineFunction &MF) const override;
void eliminateFrameIndex(MachineBasicBlock::iterator II, void eliminateFrameIndex(MachineBasicBlock::iterator II,
int SPAdj, unsigned FIOperandNum, int SPAdj, unsigned FIOperandNum,
RegScavenger *RS = nullptr) const; RegScavenger *RS = nullptr) const override;
/// determineFrameLayout - Determine the size of the frame and maximum call /// determineFrameLayout - Determine the size of the frame and maximum call
/// frame size. /// frame size.
@ -66,17 +66,17 @@ struct HexagonRegisterInfo : public HexagonGenRegisterInfo {
/// requiresRegisterScavenging - returns true since we may need scavenging for /// requiresRegisterScavenging - returns true since we may need scavenging for
/// a temporary register when generating hardware loop instructions. /// a temporary register when generating hardware loop instructions.
bool requiresRegisterScavenging(const MachineFunction &MF) const { bool requiresRegisterScavenging(const MachineFunction &MF) const override {
return true; return true;
} }
bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const { bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override {
return true; return true;
} }
// Debug information queries. // Debug information queries.
unsigned getRARegister() const; unsigned getRARegister() const;
unsigned getFrameRegister(const MachineFunction &MF) const; unsigned getFrameRegister(const MachineFunction &MF) const override;
unsigned getFrameRegister() const; unsigned getFrameRegister() const;
unsigned getStackRegister() const; unsigned getStackRegister() const;
}; };

6
lib/Target/Hexagon/HexagonRemoveSZExtArgs.cpp
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@ -33,13 +33,13 @@ namespace {
HexagonRemoveExtendArgs() : FunctionPass(ID) { HexagonRemoveExtendArgs() : FunctionPass(ID) {
initializeHexagonRemoveExtendArgsPass(*PassRegistry::getPassRegistry()); initializeHexagonRemoveExtendArgsPass(*PassRegistry::getPassRegistry());
} }
virtual bool runOnFunction(Function &F); bool runOnFunction(Function &F) override;
const char *getPassName() const { const char *getPassName() const override {
return "Remove sign extends"; return "Remove sign extends";
} }
virtual void getAnalysisUsage(AnalysisUsage &AU) const { void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.addRequired<MachineFunctionAnalysis>(); AU.addRequired<MachineFunctionAnalysis>();
AU.addPreserved<MachineFunctionAnalysis>(); AU.addPreserved<MachineFunctionAnalysis>();
AU.addPreserved("stack-protector"); AU.addPreserved("stack-protector");

3
lib/Target/Hexagon/HexagonSelectionDAGInfo.h
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@ -25,14 +25,13 @@ public:
explicit HexagonSelectionDAGInfo(const HexagonTargetMachine &TM); explicit HexagonSelectionDAGInfo(const HexagonTargetMachine &TM);
~HexagonSelectionDAGInfo(); ~HexagonSelectionDAGInfo();
virtual
SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc dl, SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc dl,
SDValue Chain, SDValue Chain,
SDValue Dst, SDValue Src, SDValue Dst, SDValue Src,
SDValue Size, unsigned Align, SDValue Size, unsigned Align,
bool isVolatile, bool AlwaysInline, bool isVolatile, bool AlwaysInline,
MachinePointerInfo DstPtrInfo, MachinePointerInfo DstPtrInfo,
MachinePointerInfo SrcPtrInfo) const; MachinePointerInfo SrcPtrInfo) const override;
}; };
} }

4
lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp
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@ -55,10 +55,10 @@ class HexagonSplitConst32AndConst64 : public MachineFunctionPass {
HexagonSplitConst32AndConst64(const HexagonTargetMachine& TM) HexagonSplitConst32AndConst64(const HexagonTargetMachine& TM)
: MachineFunctionPass(ID), QTM(TM), QST(*TM.getSubtargetImpl()) {} : MachineFunctionPass(ID), QTM(TM), QST(*TM.getSubtargetImpl()) {}
const char *getPassName() const { const char *getPassName() const override {
return "Hexagon Split Const32s and Const64s"; return "Hexagon Split Const32s and Const64s";
} }
bool runOnMachineFunction(MachineFunction &Fn); bool runOnMachineFunction(MachineFunction &Fn) override;
}; };

4
lib/Target/Hexagon/HexagonSplitTFRCondSets.cpp
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@ -68,10 +68,10 @@ class HexagonSplitTFRCondSets : public MachineFunctionPass {
initializeHexagonSplitTFRCondSetsPass(*PassRegistry::getPassRegistry()); initializeHexagonSplitTFRCondSetsPass(*PassRegistry::getPassRegistry());
} }
const char *getPassName() const { const char *getPassName() const override {
return "Hexagon Split TFRCondSets"; return "Hexagon Split TFRCondSets";
} }
bool runOnMachineFunction(MachineFunction &Fn); bool runOnMachineFunction(MachineFunction &Fn) override;
}; };

14
lib/Target/Hexagon/HexagonTargetMachine.cpp
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@ -113,16 +113,16 @@ public:
return getTM<HexagonTargetMachine>(); return getTM<HexagonTargetMachine>();
} }
virtual ScheduleDAGInstrs * ScheduleDAGInstrs *
createMachineScheduler(MachineSchedContext *C) const { createMachineScheduler(MachineSchedContext *C) const override {
return createVLIWMachineSched(C); return createVLIWMachineSched(C);
} }
virtual bool addInstSelector(); bool addInstSelector() override;
virtual bool addPreRegAlloc(); bool addPreRegAlloc() override;
virtual bool addPostRegAlloc(); bool addPostRegAlloc() override;
virtual bool addPreSched2(); bool addPreSched2() override;
virtual bool addPreEmitPass(); bool addPreEmitPass() override;
}; };
} // namespace } // namespace

20
lib/Target/Hexagon/HexagonTargetMachine.h
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@ -41,39 +41,39 @@ public:
Reloc::Model RM, CodeModel::Model CM, Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL); CodeGenOpt::Level OL);
virtual const HexagonInstrInfo *getInstrInfo() const { const HexagonInstrInfo *getInstrInfo() const override {
return &InstrInfo; return &InstrInfo;
} }
virtual const HexagonSubtarget *getSubtargetImpl() const { const HexagonSubtarget *getSubtargetImpl() const override {
return &Subtarget; return &Subtarget;
} }
virtual const HexagonRegisterInfo *getRegisterInfo() const { const HexagonRegisterInfo *getRegisterInfo() const override {
return &InstrInfo.getRegisterInfo(); return &InstrInfo.getRegisterInfo();
} }
virtual const InstrItineraryData* getInstrItineraryData() const { const InstrItineraryData* getInstrItineraryData() const override {
return InstrItins; return InstrItins;
} }
virtual const HexagonTargetLowering* getTargetLowering() const { const HexagonTargetLowering* getTargetLowering() const override {
return &TLInfo; return &TLInfo;
} }
virtual const HexagonFrameLowering* getFrameLowering() const { const HexagonFrameLowering* getFrameLowering() const override {
return &FrameLowering; return &FrameLowering;
} }
virtual const HexagonSelectionDAGInfo* getSelectionDAGInfo() const { const HexagonSelectionDAGInfo* getSelectionDAGInfo() const override {
return &TSInfo; return &TSInfo;
} }
virtual const DataLayout *getDataLayout() const { return &DL; } const DataLayout *getDataLayout() const override { return &DL; }
static unsigned getModuleMatchQuality(const Module &M); static unsigned getModuleMatchQuality(const Module &M);
// Pass Pipeline Configuration. // Pass Pipeline Configuration.
virtual bool addPassesForOptimizations(PassManagerBase &PM); virtual bool addPassesForOptimizations(PassManagerBase &PM) final;
virtual TargetPassConfig *createPassConfig(PassManagerBase &PM); TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
}; };
extern bool flag_aligned_memcpy; extern bool flag_aligned_memcpy;

19
lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
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@ -70,7 +70,7 @@ namespace {
initializeHexagonPacketizerPass(*PassRegistry::getPassRegistry()); initializeHexagonPacketizerPass(*PassRegistry::getPassRegistry());
} }
void getAnalysisUsage(AnalysisUsage &AU) const { void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.setPreservesCFG(); AU.setPreservesCFG();
AU.addRequired<MachineDominatorTree>(); AU.addRequired<MachineDominatorTree>();
AU.addRequired<MachineBranchProbabilityInfo>(); AU.addRequired<MachineBranchProbabilityInfo>();
@ -80,11 +80,11 @@ namespace {
MachineFunctionPass::getAnalysisUsage(AU); MachineFunctionPass::getAnalysisUsage(AU);
} }
const char *getPassName() const { const char *getPassName() const override {
return "Hexagon Packetizer"; return "Hexagon Packetizer";
} }
bool runOnMachineFunction(MachineFunction &Fn); bool runOnMachineFunction(MachineFunction &Fn) override;
}; };
char HexagonPacketizer::ID = 0; char HexagonPacketizer::ID = 0;
@ -122,24 +122,25 @@ namespace {
const MachineBranchProbabilityInfo *MBPI); const MachineBranchProbabilityInfo *MBPI);
// initPacketizerState - initialize some internal flags. // initPacketizerState - initialize some internal flags.
void initPacketizerState(); void initPacketizerState() override;
// ignorePseudoInstruction - Ignore bundling of pseudo instructions. // ignorePseudoInstruction - Ignore bundling of pseudo instructions.
bool ignorePseudoInstruction(MachineInstr *MI, MachineBasicBlock *MBB); bool ignorePseudoInstruction(MachineInstr *MI,
MachineBasicBlock *MBB) override;
// isSoloInstruction - return true if instruction MI can not be packetized // isSoloInstruction - return true if instruction MI can not be packetized
// with any other instruction, which means that MI itself is a packet. // with any other instruction, which means that MI itself is a packet.
bool isSoloInstruction(MachineInstr *MI); bool isSoloInstruction(MachineInstr *MI) override;
// isLegalToPacketizeTogether - Is it legal to packetize SUI and SUJ // isLegalToPacketizeTogether - Is it legal to packetize SUI and SUJ
// together. // together.
bool isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ); bool isLegalToPacketizeTogether(SUnit *SUI, SUnit *SUJ) override;
// isLegalToPruneDependencies - Is it legal to prune dependece between SUI // isLegalToPruneDependencies - Is it legal to prune dependece between SUI
// and SUJ. // and SUJ.
bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ); bool isLegalToPruneDependencies(SUnit *SUI, SUnit *SUJ) override;
MachineBasicBlock::iterator addToPacket(MachineInstr *MI); MachineBasicBlock::iterator addToPacket(MachineInstr *MI) override;
private: private:
bool IsCallDependent(MachineInstr* MI, SDep::Kind DepType, unsigned DepReg); bool IsCallDependent(MachineInstr* MI, SDep::Kind DepType, unsigned DepReg);
bool PromoteToDotNew(MachineInstr* MI, SDep::Kind DepType, bool PromoteToDotNew(MachineInstr* MI, SDep::Kind DepType,

2
lib/Target/Hexagon/InstPrinter/HexagonInstPrinter.h
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@ -27,7 +27,7 @@ namespace llvm {
const MCRegisterInfo &MRI) const MCRegisterInfo &MRI)
: MCInstPrinter(MAI, MII, MRI), MII(MII) {} : MCInstPrinter(MAI, MII, MRI), MII(MII) {}
virtual void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot); void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot) override;
void printInst(const HexagonMCInst *MI, raw_ostream &O, StringRef Annot); void printInst(const HexagonMCInst *MI, raw_ostream &O, StringRef Annot);
virtual StringRef getOpcodeName(unsigned Opcode) const; virtual StringRef getOpcodeName(unsigned Opcode) const;
void printInstruction(const MCInst *MI, raw_ostream &O); void printInstruction(const MCInst *MI, raw_ostream &O);

2
lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.h
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@ -19,7 +19,7 @@
namespace llvm { namespace llvm {
class HexagonMCAsmInfo : public MCAsmInfoELF { class HexagonMCAsmInfo : public MCAsmInfoELF {
virtual void anchor(); void anchor() override;
public: public:
explicit HexagonMCAsmInfo(StringRef TT); explicit HexagonMCAsmInfo(StringRef TT);
}; };