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[Stackmap] Liveness Analysis Pass
This optional register liveness analysis pass can be enabled with either -enable-stackmap-liveness, -enable-patchpoint-liveness, or both. The pass traverses each basic block in a machine function. For each basic block the instructions are processed in reversed order and if a patchpoint or stackmap instruction is encountered the current live-out register set is encoded as a register mask and attached to the instruction. Later on during stackmap generation the live-out register mask is processed and also emitted as part of the stackmap. This information is optional and intended for optimization purposes only. This will enable a client of the stackmap to reason about the registers it can use and which registers need to be preserved. Reviewed by Andy git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197317 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -68,10 +68,10 @@ unsigned PatchPointOpers::getNextScratchIdx(unsigned StartIdx) const {
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std::pair<StackMaps::Location, MachineInstr::const_mop_iterator>
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StackMaps::parseOperand(MachineInstr::const_mop_iterator MOI,
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MachineInstr::const_mop_iterator MOE) {
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MachineInstr::const_mop_iterator MOE) const {
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const MachineOperand &MOP = *MOI;
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assert(!MOP.isRegMask() && (!MOP.isReg() || !MOP.isImplicit()) &&
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"Register mask and implicit operands should not be processed.");
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assert((!MOP.isReg() || !MOP.isImplicit()) &&
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"Implicit operands should not be processed.");
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if (MOP.isImm()) {
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// Verify anyregcc
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@ -106,6 +106,9 @@ StackMaps::parseOperand(MachineInstr::const_mop_iterator MOI,
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}
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}
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if (MOP.isRegMask() || MOP.isRegLiveOut())
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return std::make_pair(Location(), ++MOI);
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// Otherwise this is a reg operand. The physical register number will
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// ultimately be encoded as a DWARF regno. The stack map also records the size
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// of a spill slot that can hold the register content. (The runtime can
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@ -120,6 +123,65 @@ StackMaps::parseOperand(MachineInstr::const_mop_iterator MOI,
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Location(Location::Register, RC->getSize(), MOP.getReg(), 0), ++MOI);
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}
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/// Go up the super-register chain until we hit a valid dwarf register number.
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static unsigned short getDwarfRegNum(unsigned Reg, const MCRegisterInfo &MCRI,
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const TargetRegisterInfo *TRI) {
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int RegNo = MCRI.getDwarfRegNum(Reg, false);
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for (MCSuperRegIterator SR(Reg, TRI);
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SR.isValid() && RegNo < 0; ++SR)
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RegNo = TRI->getDwarfRegNum(*SR, false);
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assert(RegNo >= 0 && "Invalid Dwarf register number.");
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return (unsigned short) RegNo;
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}
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/// Create a live-out register record for the given register Reg.
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StackMaps::LiveOutReg
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StackMaps::createLiveOutReg(unsigned Reg, const MCRegisterInfo &MCRI,
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const TargetRegisterInfo *TRI) const {
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unsigned RegNo = getDwarfRegNum(Reg, MCRI, TRI);
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unsigned Size = TRI->getMinimalPhysRegClass(Reg)->getSize();
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return LiveOutReg(Reg, RegNo, Size);
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}
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/// Parse the register live-out mask and return a vector of live-out registers
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/// that need to be recorded in the stackmap.
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StackMaps::LiveOutVec
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StackMaps::parseRegisterLiveOutMask(const uint32_t *Mask) const {
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assert(Mask && "No register mask specified");
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const TargetRegisterInfo *TRI = AP.TM.getRegisterInfo();
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MCContext &OutContext = AP.OutStreamer.getContext();
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const MCRegisterInfo &MCRI = *OutContext.getRegisterInfo();
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LiveOutVec LiveOuts;
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// Create a LiveOutReg for each bit that is set in the register mask.
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for (unsigned Reg = 0, NumRegs = TRI->getNumRegs(); Reg != NumRegs; ++Reg)
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if ((Mask[Reg / 32] >> Reg % 32) & 1)
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LiveOuts.push_back(createLiveOutReg(Reg, MCRI, TRI));
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// We don't need to keep track of a register if its super-register is already
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// in the list. Merge entries that refer to the same dwarf register and use
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// the maximum size that needs to be spilled.
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std::sort(LiveOuts.begin(), LiveOuts.end());
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for (LiveOutVec::iterator I = LiveOuts.begin(), E = LiveOuts.end();
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I != E; ++I) {
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for (LiveOutVec::iterator II = next(I); II != E; ++II) {
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if (I->RegNo != II->RegNo) {
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// Skip all the now invalid entries.
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I = --II;
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break;
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}
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I->Size = std::max(I->Size, II->Size);
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if (TRI->isSuperRegister(I->Reg, II->Reg))
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I->Reg = II->Reg;
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II->MarkInvalid();
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}
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}
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LiveOuts.erase(std::remove_if(LiveOuts.begin(), LiveOuts.end(),
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LiveOutReg::IsInvalid), LiveOuts.end());
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return LiveOuts;
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}
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void StackMaps::recordStackMapOpers(const MachineInstr &MI, uint64_t ID,
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MachineInstr::const_mop_iterator MOI,
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MachineInstr::const_mop_iterator MOE,
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@ -129,7 +191,8 @@ void StackMaps::recordStackMapOpers(const MachineInstr &MI, uint64_t ID,
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MCSymbol *MILabel = OutContext.CreateTempSymbol();
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AP.OutStreamer.EmitLabel(MILabel);
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LocationVec CallsiteLocs;
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LocationVec Locations;
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LiveOutVec LiveOuts;
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if (recordResult) {
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std::pair<Location, MachineInstr::const_mop_iterator> ParseResult =
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@ -138,7 +201,7 @@ void StackMaps::recordStackMapOpers(const MachineInstr &MI, uint64_t ID,
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Location &Loc = ParseResult.first;
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assert(Loc.LocType == Location::Register &&
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"Stackmap return location must be a register.");
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CallsiteLocs.push_back(Loc);
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Locations.push_back(Loc);
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}
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while (MOI != MOE) {
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@ -151,7 +214,9 @@ void StackMaps::recordStackMapOpers(const MachineInstr &MI, uint64_t ID,
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Loc.Offset = ConstPool.getConstantIndex(Loc.Offset);
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}
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CallsiteLocs.push_back(Loc);
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// Skip the register mask and register live-out mask
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if (Loc.LocType != Location::Unprocessed)
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Locations.push_back(Loc);
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}
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const MCExpr *CSOffsetExpr = MCBinaryExpr::CreateSub(
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@ -159,21 +224,23 @@ void StackMaps::recordStackMapOpers(const MachineInstr &MI, uint64_t ID,
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MCSymbolRefExpr::Create(AP.CurrentFnSym, OutContext),
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OutContext);
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CSInfos.push_back(CallsiteInfo(CSOffsetExpr, ID, CallsiteLocs));
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if (MOI->isRegLiveOut())
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LiveOuts = parseRegisterLiveOutMask(MOI->getRegLiveOut());
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CSInfos.push_back(CallsiteInfo(CSOffsetExpr, ID, Locations, LiveOuts));
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}
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static MachineInstr::const_mop_iterator
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getStackMapEndMOP(MachineInstr::const_mop_iterator MOI,
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MachineInstr::const_mop_iterator MOE) {
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for (; MOI != MOE; ++MOI)
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if (MOI->isRegMask() || (MOI->isReg() && MOI->isImplicit()))
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if (MOI->isRegLiveOut() || (MOI->isReg() && MOI->isImplicit()))
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break;
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return MOI;
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}
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void StackMaps::recordStackMap(const MachineInstr &MI) {
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assert(MI.getOpcode() == TargetOpcode::STACKMAP && "exected stackmap");
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assert(MI.getOpcode() == TargetOpcode::STACKMAP && "expected stackmap");
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int64_t ID = MI.getOperand(0).getImm();
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recordStackMapOpers(MI, ID, llvm::next(MI.operands_begin(), 2),
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@ -182,7 +249,7 @@ void StackMaps::recordStackMap(const MachineInstr &MI) {
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}
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void StackMaps::recordPatchPoint(const MachineInstr &MI) {
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assert(MI.getOpcode() == TargetOpcode::PATCHPOINT && "exected stackmap");
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assert(MI.getOpcode() == TargetOpcode::PATCHPOINT && "expected patchpoint");
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PatchPointOpers opers(&MI);
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int64_t ID = opers.getMetaOper(PatchPointOpers::IDPos).getImm();
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@ -221,6 +288,11 @@ void StackMaps::recordPatchPoint(const MachineInstr &MI) {
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/// uint16 : Dwarf RegNum
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/// int32 : Offset
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/// }
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/// uint16 : NumLiveOuts
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/// LiveOuts[NumLiveOuts]
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/// uint16 : Dwarf RegNum
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/// uint8 : Reserved
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/// uint8 : Size in Bytes
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/// }
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///
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/// Location Encoding, Type, Value:
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@ -273,6 +345,7 @@ void StackMaps::serializeToStackMapSection() {
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uint64_t CallsiteID = CSII->ID;
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const LocationVec &CSLocs = CSII->Locations;
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const LiveOutVec &LiveOuts = CSII->LiveOuts;
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DEBUG(dbgs() << WSMP << "callsite " << CallsiteID << "\n");
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@ -280,11 +353,12 @@ void StackMaps::serializeToStackMapSection() {
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// runtime than crash in case of in-process compilation. Currently, we do
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// simple overflow checks, but we may eventually communicate other
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// compilation errors this way.
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if (CSLocs.size() > UINT16_MAX) {
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AP.OutStreamer.EmitIntValue(UINT32_MAX, 8); // Invalid ID.
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if (CSLocs.size() > UINT16_MAX || LiveOuts.size() > UINT16_MAX) {
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AP.OutStreamer.EmitIntValue(UINT64_MAX, 8); // Invalid ID.
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AP.OutStreamer.EmitValue(CSII->CSOffsetExpr, 4);
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AP.OutStreamer.EmitIntValue(0, 2); // Reserved.
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AP.OutStreamer.EmitIntValue(0, 2); // 0 locations.
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AP.OutStreamer.EmitIntValue(0, 2); // 0 live-out registers.
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continue;
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}
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@ -361,6 +435,24 @@ void StackMaps::serializeToStackMapSection() {
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AP.OutStreamer.EmitIntValue(RegNo, 2);
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AP.OutStreamer.EmitIntValue(Offset, 4);
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}
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DEBUG(dbgs() << WSMP << " has " << LiveOuts.size()
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<< " live-out registers\n");
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AP.OutStreamer.EmitIntValue(LiveOuts.size(), 2);
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operIdx = 0;
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for (LiveOutVec::const_iterator LI = LiveOuts.begin(), LE = LiveOuts.end();
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LI != LE; ++LI, ++operIdx) {
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DEBUG(dbgs() << WSMP << " LO " << operIdx << ": "
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<< MCRI.getName(LI->Reg)
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<< " [encoding: .short " << LI->RegNo
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<< ", .byte 0, .byte " << LI->Size << "]\n");
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AP.OutStreamer.EmitIntValue(LI->RegNo, 2);
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AP.OutStreamer.EmitIntValue(0, 1);
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AP.OutStreamer.EmitIntValue(LI->Size, 1);
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}
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}
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AP.OutStreamer.AddBlankLine();
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