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R600: Expand vector sin and cos.

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v2: move code to AMDGPUISelLowering.cpp
    squash with tests (both EG and SI)

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207845 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tom Stellard 2014-05-02 15:41:47 +00:00
parent 1d6859256c
commit ab2fed6622
3 changed files with 67 additions and 22 deletions
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2
lib/Target/R600/AMDGPUISelLowering.cpp
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@ -246,6 +246,7 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
MVT::SimpleValueType VT = FloatTypes[x];
setOperationAction(ISD::FABS, VT, Expand);
setOperationAction(ISD::FADD, VT, Expand);
setOperationAction(ISD::FCOS, VT, Expand);
setOperationAction(ISD::FDIV, VT, Expand);
setOperationAction(ISD::FPOW, VT, Expand);
setOperationAction(ISD::FFLOOR, VT, Expand);
@ -253,6 +254,7 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
setOperationAction(ISD::FMUL, VT, Expand);
setOperationAction(ISD::FRINT, VT, Expand);
setOperationAction(ISD::FSQRT, VT, Expand);
setOperationAction(ISD::FSIN, VT, Expand);
setOperationAction(ISD::FSUB, VT, Expand);
setOperationAction(ISD::SELECT, VT, Expand);
}

43
test/CodeGen/R600/llvm.cos.ll
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@ -1,19 +1,40 @@
;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s -check-prefix=EG -check-prefix=FUNC
;RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s -check-prefix=SI -check-prefix=FUNC
;CHECK: MULADD_IEEE *
;CHECK: FRACT *
;CHECK: ADD *
;CHECK: COS * T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
;FUNC-LABEL: test
;EG: MULADD_IEEE *
;EG: FRACT *
;EG: ADD *
;EG: COS * T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
;EG-NOT: COS
;SI: V_COS_F32
;SI-NOT: V_COS_F32
define void @test(<4 x float> inreg %reg0) #0 {
%r0 = extractelement <4 x float> %reg0, i32 0
%r1 = call float @llvm.cos.f32(float %r0)
%vec = insertelement <4 x float> undef, float %r1, i32 0
call void @llvm.R600.store.swizzle(<4 x float> %vec, i32 0, i32 0)
define void @test(float addrspace(1)* %out, float %x) #1 {
%cos = call float @llvm.cos.f32(float %x)
store float %cos, float addrspace(1)* %out
ret void
}
;FUNC-LABEL: testv
;EG: COS * T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
;EG: COS * T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
;EG: COS * T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
;EG: COS * T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
;EG-NOT: COS
;SI: V_COS_F32
;SI: V_COS_F32
;SI: V_COS_F32
;SI: V_COS_F32
;SI-NOT: V_COS_F32
define void @testv(<4 x float> addrspace(1)* %out, <4 x float> inreg %vx) #1 {
%cos = call <4 x float> @llvm.cos.v4f32(<4 x float> %vx)
store <4 x float> %cos, <4 x float> addrspace(1)* %out
ret void
}
declare float @llvm.cos.f32(float) readnone
declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
declare <4 x float> @llvm.cos.v4f32(<4 x float>) readnone
attributes #0 = { "ShaderType"="0" }

44
test/CodeGen/R600/llvm.sin.ll
View File

@ -1,19 +1,41 @@
;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s -check-prefix=EG -check-prefix=FUNC
;RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s -check-prefix=SI -check-prefix=FUNC
;CHECK: MULADD_IEEE *
;CHECK: FRACT *
;CHECK: ADD *
;CHECK: SIN * T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
;FUNC-LABEL: test
;EG: MULADD_IEEE *
;EG: FRACT *
;EG: ADD *
;EG: SIN * T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
;EG-NOT: SIN
;SI: V_MUL_F32
;SI: V_SIN_F32
;SI-NOT: V_SIN_F32
define void @test(<4 x float> inreg %reg0) #0 {
%r0 = extractelement <4 x float> %reg0, i32 0
%r1 = call float @llvm.sin.f32( float %r0)
%vec = insertelement <4 x float> undef, float %r1, i32 0
call void @llvm.R600.store.swizzle(<4 x float> %vec, i32 0, i32 0)
define void @test(float addrspace(1)* %out, float %x) #1 {
%sin = call float @llvm.sin.f32(float %x)
store float %sin, float addrspace(1)* %out
ret void
}
;FUNC-LABEL: testv
;EG: SIN * T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
;EG: SIN * T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
;EG: SIN * T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
;EG: SIN * T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
;EG-NOT: SIN
;SI: V_SIN_F32
;SI: V_SIN_F32
;SI: V_SIN_F32
;SI: V_SIN_F32
;SI-NOT: V_SIN_F32
define void @testv(<4 x float> addrspace(1)* %out, <4 x float> %vx) #1 {
%sin = call <4 x float> @llvm.sin.v4f32( <4 x float> %vx)
store <4 x float> %sin, <4 x float> addrspace(1)* %out
ret void
}
declare float @llvm.sin.f32(float) readnone
declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
declare <4 x float> @llvm.sin.v4f32(<4 x float>) readnone
attributes #0 = { "ShaderType"="0" }