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https://github.com/c64scene-ar/llvm-6502.git
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Try approach to moving call address load inside of callseq_start. Now it's done during the preprocess of x86 isel. callseq_start's chain is changed to load's chain node; while load's chain is the last of callseq_start or the loads or copytoreg nodes inserted to move arguments to the right spot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55338 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
parent
140a8bb006
commit
ab6c3bb44d
@ -373,12 +373,12 @@ bool X86DAGToDAGISel::CanBeFoldedBy(SDNode *N, SDNode *U, SDNode *Root) const {
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/// load's chain result.
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static void MoveBelowTokenFactor(SelectionDAG *CurDAG, SDValue Load,
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SDValue Store, SDValue TF) {
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std::vector<SDValue> Ops;
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SmallVector<SDValue, 4> Ops;
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for (unsigned i = 0, e = TF.Val->getNumOperands(); i != e; ++i)
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if (Load.Val == TF.Val->getOperand(i).Val)
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Ops.push_back(Load.Val->getOperand(0));
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if (Load.Val == TF.getOperand(i).Val)
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Ops.push_back(Load.getOperand(0));
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else
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Ops.push_back(TF.Val->getOperand(i));
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Ops.push_back(TF.getOperand(i));
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CurDAG->UpdateNodeOperands(TF, &Ops[0], Ops.size());
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CurDAG->UpdateNodeOperands(Load, TF, Load.getOperand(1), Load.getOperand(2));
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CurDAG->UpdateNodeOperands(Store, Load.getValue(1), Store.getOperand(1),
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@ -411,6 +411,49 @@ static bool isRMWLoad(SDValue N, SDValue Chain, SDValue Address,
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return false;
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}
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/// MoveBelowCallSeqStart - Replace CALLSEQ_START operand with load's chain
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/// operand and move load below the call's chain operand.
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static void MoveBelowCallSeqStart(SelectionDAG *CurDAG, SDValue Load,
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SDValue Call, SDValue Chain) {
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SmallVector<SDValue, 8> Ops;
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for (unsigned i = 0, e = Chain.Val->getNumOperands(); i != e; ++i)
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if (Load.Val == Chain.getOperand(i).Val)
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Ops.push_back(Load.getOperand(0));
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else
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Ops.push_back(Chain.getOperand(i));
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CurDAG->UpdateNodeOperands(Chain, &Ops[0], Ops.size());
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CurDAG->UpdateNodeOperands(Load, Call.getOperand(0),
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Load.getOperand(1), Load.getOperand(2));
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Ops.clear();
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Ops.push_back(SDValue(Load.Val, 1));
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for (unsigned i = 1, e = Call.Val->getNumOperands(); i != e; ++i)
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Ops.push_back(Call.getOperand(i));
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CurDAG->UpdateNodeOperands(Call, &Ops[0], Ops.size());
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}
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/// isCalleeLoad - Return true if call address is a load and it can be
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/// moved below CALLSEQ_START and the chains leading up to the call.
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/// Return the CALLSEQ_START by reference as a second output.
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static bool isCalleeLoad(SDValue Callee, SDValue &Chain) {
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if (Callee.Val == Chain.Val || !Callee.hasOneUse())
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return false;
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LoadSDNode *LD = dyn_cast<LoadSDNode>(Callee.Val);
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if (!LD ||
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LD->isVolatile() ||
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LD->getAddressingMode() != ISD::UNINDEXED ||
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LD->getExtensionType() != ISD::NON_EXTLOAD)
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return false;
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// Now let's find the callseq_start.
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while (Chain.getOpcode() != ISD::CALLSEQ_START) {
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if (!Chain.hasOneUse())
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return false;
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Chain = Chain.getOperand(0);
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}
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return Chain.getOperand(0).Val == Callee.Val;
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}
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/// PreprocessForRMW - Preprocess the DAG to make instruction selection better.
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/// This is only run if not in -fast mode (aka -O0).
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/// This allows the instruction selector to pick more read-modify-write
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@ -454,9 +497,39 @@ static bool isRMWLoad(SDValue N, SDValue Chain, SDValue Address,
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void X86DAGToDAGISel::PreprocessForRMW() {
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for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
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E = CurDAG->allnodes_end(); I != E; ++I) {
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if (I->getOpcode() == X86ISD::CALL) {
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/// Also try moving call address load from outside callseq_start to just
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/// before the call to allow it to be folded.
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///
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/// [Load chain]
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/// ^
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/// |
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/// [Load]
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/// ^ ^
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/// | |
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/// / \--
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/// / |
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///[CALLSEQ_START] |
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/// ^ |
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/// | |
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/// [LOAD/C2Reg] |
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/// | |
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/// \ /
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/// \ /
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/// [CALL]
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SDValue Chain = I->getOperand(0);
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SDValue Load = I->getOperand(1);
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if (!isCalleeLoad(Load, Chain))
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continue;
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MoveBelowCallSeqStart(CurDAG, Load, SDValue(I, 0), Chain);
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++NumLoadMoved;
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continue;
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}
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if (!ISD::isNON_TRUNCStore(I))
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continue;
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SDValue Chain = I->getOperand(0);
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if (Chain.Val->getOpcode() != ISD::TokenFactor)
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continue;
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@ -471,35 +544,35 @@ void X86DAGToDAGISel::PreprocessForRMW() {
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SDValue Load;
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unsigned Opcode = N1.Val->getOpcode();
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switch (Opcode) {
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case ISD::ADD:
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case ISD::MUL:
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case ISD::AND:
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case ISD::OR:
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case ISD::XOR:
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case ISD::ADDC:
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case ISD::ADDE:
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case ISD::VECTOR_SHUFFLE: {
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SDValue N10 = N1.getOperand(0);
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SDValue N11 = N1.getOperand(1);
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RModW = isRMWLoad(N10, Chain, N2, Load);
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if (!RModW)
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RModW = isRMWLoad(N11, Chain, N2, Load);
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break;
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}
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case ISD::SUB:
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case ISD::SHL:
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case ISD::SRA:
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case ISD::SRL:
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case ISD::ROTL:
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case ISD::ROTR:
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case ISD::SUBC:
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case ISD::SUBE:
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case X86ISD::SHLD:
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case X86ISD::SHRD: {
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SDValue N10 = N1.getOperand(0);
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RModW = isRMWLoad(N10, Chain, N2, Load);
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break;
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}
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case ISD::ADD:
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case ISD::MUL:
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case ISD::AND:
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case ISD::OR:
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case ISD::XOR:
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case ISD::ADDC:
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case ISD::ADDE:
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case ISD::VECTOR_SHUFFLE: {
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SDValue N10 = N1.getOperand(0);
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SDValue N11 = N1.getOperand(1);
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RModW = isRMWLoad(N10, Chain, N2, Load);
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if (!RModW)
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RModW = isRMWLoad(N11, Chain, N2, Load);
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break;
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}
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case ISD::SUB:
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case ISD::SHL:
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case ISD::SRA:
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case ISD::SRL:
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case ISD::ROTL:
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case ISD::ROTR:
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case ISD::SUBC:
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case ISD::SUBE:
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case X86ISD::SHLD:
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case X86ISD::SHRD: {
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SDValue N10 = N1.getOperand(0);
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RModW = isRMWLoad(N10, Chain, N2, Load);
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break;
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}
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}
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if (RModW) {
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@ -1457,12 +1457,12 @@ EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
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SDValue X86TargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
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MachineFunction &MF = DAG.getMachineFunction();
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SDValue Chain = Op.getOperand(0);
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SDValue Chain = Op.getOperand(0);
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unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
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bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
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bool IsTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0
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&& CC == CallingConv::Fast && PerformTailCallOpt;
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SDValue Callee = Op.getOperand(4);
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SDValue Callee = Op.getOperand(4);
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bool Is64Bit = Subtarget->is64Bit();
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bool IsStructRet = CallIsStructReturn(Op);
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@ -1,5 +1,4 @@
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; RUN: llvm-as < %s | llc -mtriple=i386-apple-darwin | grep mov | count 1
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; XFAIL: *
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@f = external global void ()* ; <void ()**> [#uses=1]
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