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Correctly print out long branches, assert on finding pseudo instr COND_BRANCH

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Patch by Nate Begeman.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15286 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Misha Brukman 2004-07-27 18:40:39 +00:00
parent bd2c870539
commit ab96790f2c
3 changed files with 36 additions and 3 deletions
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13
lib/Target/PowerPC/PPC32AsmPrinter.cpp
View File

@ -507,7 +507,10 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
// appropriate number of args that the assembler expects. This is because // appropriate number of args that the assembler expects. This is because
// may have many arguments appended to record the uses of registers that are // may have many arguments appended to record the uses of registers that are
// holding arguments to the called function. // holding arguments to the called function.
if (Opcode == PPC32::IMPLICIT_DEF) { if (Opcode == PPC32::COND_BRANCH) {
std::cerr << "Error: untranslated conditional branch psuedo instruction!\n";
abort();
} else if (Opcode == PPC32::IMPLICIT_DEF) {
O << "; IMPLICIT DEF "; O << "; IMPLICIT DEF ";
printOp(MI->getOperand(0)); printOp(MI->getOperand(0));
O << "\n"; O << "\n";
@ -569,10 +572,18 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
O << ")\n"; O << ")\n";
} else { } else {
for (i = 0; i < ArgCount; ++i) { for (i = 0; i < ArgCount; ++i) {
// addi and friends
if (i == 1 && ArgCount == 3 && ArgType[2] == PPC32II::Simm16 && if (i == 1 && ArgCount == 3 && ArgType[2] == PPC32II::Simm16 &&
MI->getOperand(1).hasAllocatedReg() && MI->getOperand(1).hasAllocatedReg() &&
MI->getOperand(1).getReg() == PPC32::R0) { MI->getOperand(1).getReg() == PPC32::R0) {
O << "0"; O << "0";
// for long branch support, bc $+8
} else if (i == 1 && ArgCount == 2 && MI->getOperand(1).isImmediate() &&
TII.isBranch(MI->getOpcode())) {
O << "$+8";
assert(8 == MI->getOperand(i).getImmedValue()
&& "branch off PC not to pc+8?");
//printOp(MI->getOperand(i));
} else { } else {
printOp(MI->getOperand(i)); printOp(MI->getOperand(i));
} }

13
lib/Target/PowerPC/PPCAsmPrinter.cpp
View File

@ -507,7 +507,10 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
// appropriate number of args that the assembler expects. This is because // appropriate number of args that the assembler expects. This is because
// may have many arguments appended to record the uses of registers that are // may have many arguments appended to record the uses of registers that are
// holding arguments to the called function. // holding arguments to the called function.
if (Opcode == PPC32::IMPLICIT_DEF) { if (Opcode == PPC32::COND_BRANCH) {
std::cerr << "Error: untranslated conditional branch psuedo instruction!\n";
abort();
} else if (Opcode == PPC32::IMPLICIT_DEF) {
O << "; IMPLICIT DEF "; O << "; IMPLICIT DEF ";
printOp(MI->getOperand(0)); printOp(MI->getOperand(0));
O << "\n"; O << "\n";
@ -569,10 +572,18 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
O << ")\n"; O << ")\n";
} else { } else {
for (i = 0; i < ArgCount; ++i) { for (i = 0; i < ArgCount; ++i) {
// addi and friends
if (i == 1 && ArgCount == 3 && ArgType[2] == PPC32II::Simm16 && if (i == 1 && ArgCount == 3 && ArgType[2] == PPC32II::Simm16 &&
MI->getOperand(1).hasAllocatedReg() && MI->getOperand(1).hasAllocatedReg() &&
MI->getOperand(1).getReg() == PPC32::R0) { MI->getOperand(1).getReg() == PPC32::R0) {
O << "0"; O << "0";
// for long branch support, bc $+8
} else if (i == 1 && ArgCount == 2 && MI->getOperand(1).isImmediate() &&
TII.isBranch(MI->getOpcode())) {
O << "$+8";
assert(8 == MI->getOperand(i).getImmedValue()
&& "branch off PC not to pc+8?");
//printOp(MI->getOperand(i));
} else { } else {
printOp(MI->getOperand(i)); printOp(MI->getOperand(i));
} }

13
lib/Target/PowerPC/PowerPCAsmPrinter.cpp
View File

@ -507,7 +507,10 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
// appropriate number of args that the assembler expects. This is because // appropriate number of args that the assembler expects. This is because
// may have many arguments appended to record the uses of registers that are // may have many arguments appended to record the uses of registers that are
// holding arguments to the called function. // holding arguments to the called function.
if (Opcode == PPC32::IMPLICIT_DEF) { if (Opcode == PPC32::COND_BRANCH) {
std::cerr << "Error: untranslated conditional branch psuedo instruction!\n";
abort();
} else if (Opcode == PPC32::IMPLICIT_DEF) {
O << "; IMPLICIT DEF "; O << "; IMPLICIT DEF ";
printOp(MI->getOperand(0)); printOp(MI->getOperand(0));
O << "\n"; O << "\n";
@ -569,10 +572,18 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
O << ")\n"; O << ")\n";
} else { } else {
for (i = 0; i < ArgCount; ++i) { for (i = 0; i < ArgCount; ++i) {
// addi and friends
if (i == 1 && ArgCount == 3 && ArgType[2] == PPC32II::Simm16 && if (i == 1 && ArgCount == 3 && ArgType[2] == PPC32II::Simm16 &&
MI->getOperand(1).hasAllocatedReg() && MI->getOperand(1).hasAllocatedReg() &&
MI->getOperand(1).getReg() == PPC32::R0) { MI->getOperand(1).getReg() == PPC32::R0) {
O << "0"; O << "0";
// for long branch support, bc $+8
} else if (i == 1 && ArgCount == 2 && MI->getOperand(1).isImmediate() &&
TII.isBranch(MI->getOpcode())) {
O << "$+8";
assert(8 == MI->getOperand(i).getImmedValue()
&& "branch off PC not to pc+8?");
//printOp(MI->getOperand(i));
} else { } else {
printOp(MI->getOperand(i)); printOp(MI->getOperand(i));
} }