From abcde265b1f8f8d29a4542bfd87ee6f8fb1537a0 Mon Sep 17 00:00:00 2001 From: Vincent Lejeune Date: Tue, 30 Apr 2013 00:14:17 +0000 Subject: [PATCH] R600: Rework Scheduling to handle difference between VLIW4 and VLIW5 chips git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180759 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/R600/Processors.td | 32 ++++++------ lib/Target/R600/R600InstrInfo.cpp | 8 +++ lib/Target/R600/R600InstrInfo.h | 3 ++ lib/Target/R600/R600Instructions.td | 81 +++++++++++++++++++++++------ lib/Target/R600/R600Schedule.td | 13 ++++- 5 files changed, 105 insertions(+), 32 deletions(-) diff --git a/lib/Target/R600/Processors.td b/lib/Target/R600/Processors.td index abefba2c730..e024e668440 100644 --- a/lib/Target/R600/Processors.td +++ b/lib/Target/R600/Processors.td @@ -13,37 +13,37 @@ class Proc Features> : Processor; -def : Proc<"", R600_EG_Itin, +def : Proc<"", R600_VLIW5_Itin, [FeatureR600ALUInst, FeatureVertexCache]>; -def : Proc<"r600", R600_EG_Itin, +def : Proc<"r600", R600_VLIW5_Itin, [FeatureR600ALUInst , FeatureVertexCache]>; -def : Proc<"rs880", R600_EG_Itin, +def : Proc<"rs880", R600_VLIW5_Itin, [FeatureR600ALUInst]>; -def : Proc<"rv670", R600_EG_Itin, +def : Proc<"rv670", R600_VLIW5_Itin, [FeatureR600ALUInst, FeatureFP64, FeatureVertexCache]>; -def : Proc<"rv710", R600_EG_Itin, +def : Proc<"rv710", R600_VLIW5_Itin, [FeatureVertexCache]>; -def : Proc<"rv730", R600_EG_Itin, +def : Proc<"rv730", R600_VLIW5_Itin, [FeatureVertexCache]>; -def : Proc<"rv770", R600_EG_Itin, +def : Proc<"rv770", R600_VLIW5_Itin, [FeatureFP64, FeatureVertexCache]>; -def : Proc<"cedar", R600_EG_Itin, +def : Proc<"cedar", R600_VLIW5_Itin, [FeatureByteAddress, FeatureImages, FeatureVertexCache]>; -def : Proc<"redwood", R600_EG_Itin, +def : Proc<"redwood", R600_VLIW5_Itin, [FeatureByteAddress, FeatureImages, FeatureVertexCache]>; -def : Proc<"sumo", R600_EG_Itin, +def : Proc<"sumo", R600_VLIW5_Itin, [FeatureByteAddress, FeatureImages]>; -def : Proc<"juniper", R600_EG_Itin, +def : Proc<"juniper", R600_VLIW5_Itin, [FeatureByteAddress, FeatureImages, FeatureVertexCache]>; -def : Proc<"cypress", R600_EG_Itin, +def : Proc<"cypress", R600_VLIW5_Itin, [FeatureByteAddress, FeatureImages, FeatureFP64, FeatureVertexCache]>; -def : Proc<"barts", R600_EG_Itin, +def : Proc<"barts", R600_VLIW5_Itin, [FeatureByteAddress, FeatureImages, FeatureVertexCache]>; -def : Proc<"turks", R600_EG_Itin, +def : Proc<"turks", R600_VLIW5_Itin, [FeatureByteAddress, FeatureImages, FeatureVertexCache]>; -def : Proc<"caicos", R600_EG_Itin, +def : Proc<"caicos", R600_VLIW5_Itin, [FeatureByteAddress, FeatureImages]>; -def : Proc<"cayman", R600_EG_Itin, +def : Proc<"cayman", R600_VLIW4_Itin, [FeatureByteAddress, FeatureImages, FeatureFP64]>;def : Proc<"SI", SI_Itin, [Feature64BitPtr, FeatureFP64]>; def : Proc<"tahiti", SI_Itin, [Feature64BitPtr, FeatureFP64]>; def : Proc<"pitcairn", SI_Itin, [Feature64BitPtr, FeatureFP64]>; diff --git a/lib/Target/R600/R600InstrInfo.cpp b/lib/Target/R600/R600InstrInfo.cpp index 3e166e6937f..b1edb137da5 100644 --- a/lib/Target/R600/R600InstrInfo.cpp +++ b/lib/Target/R600/R600InstrInfo.cpp @@ -140,6 +140,14 @@ bool R600InstrInfo::isALUInstr(unsigned Opcode) const { (TargetFlags & R600_InstFlag::OP3)); } +bool R600InstrInfo::isTransOnly(unsigned Opcode) const { + return (get(Opcode).TSFlags & R600_InstFlag::TRANS_ONLY); +} + +bool R600InstrInfo::isTransOnly(const MachineInstr *MI) const { + return isTransOnly(MI->getOpcode()); +} + bool R600InstrInfo::usesVertexCache(unsigned Opcode) const { return ST.hasVertexCache() && get(Opcode).TSFlags & R600_InstFlag::VTX_INST; } diff --git a/lib/Target/R600/R600InstrInfo.h b/lib/Target/R600/R600InstrInfo.h index 2146788604b..babe4b8fe51 100644 --- a/lib/Target/R600/R600InstrInfo.h +++ b/lib/Target/R600/R600InstrInfo.h @@ -54,6 +54,9 @@ namespace llvm { /// \returns true if this \p Opcode represents an ALU instruction. bool isALUInstr(unsigned Opcode) const; + bool isTransOnly(unsigned Opcode) const; + bool isTransOnly(const MachineInstr *MI) const; + bool usesVertexCache(unsigned Opcode) const; bool usesVertexCache(const MachineInstr *MI) const; bool usesTextureCache(unsigned Opcode) const; diff --git a/lib/Target/R600/R600Instructions.td b/lib/Target/R600/R600Instructions.td index db2080dbec9..3426831a635 100644 --- a/lib/Target/R600/R600Instructions.td +++ b/lib/Target/R600/R600Instructions.td @@ -18,6 +18,7 @@ class InstR600 pattern, : AMDGPUInst { field bits<64> Inst; + bit TransOnly = 0; bit Trig = 0; bit Op3 = 0; bit isVector = 0; @@ -35,6 +36,7 @@ class InstR600 pattern, let Pattern = pattern; let Itinerary = itin; + let TSFlags{0} = TransOnly; let TSFlags{4} = Trig; let TSFlags{5} = Op3; @@ -1301,23 +1303,38 @@ multiclass CUBE_Common inst> { class EXP_IEEE_Common inst> : R600_1OP_Helper < inst, "EXP_IEEE", fexp2 ->; +> { + let TransOnly = 1; + let Itinerary = TransALU; +} class FLT_TO_INT_Common inst> : R600_1OP_Helper < inst, "FLT_TO_INT", fp_to_sint ->; +> { + let TransOnly = 1; + let Itinerary = TransALU; +} class INT_TO_FLT_Common inst> : R600_1OP_Helper < inst, "INT_TO_FLT", sint_to_fp ->; +> { + let TransOnly = 1; + let Itinerary = TransALU; +} class FLT_TO_UINT_Common inst> : R600_1OP_Helper < inst, "FLT_TO_UINT", fp_to_uint ->; +> { + let TransOnly = 1; + let Itinerary = TransALU; +} class UINT_TO_FLT_Common inst> : R600_1OP_Helper < inst, "UINT_TO_FLT", uint_to_fp ->; +> { + let TransOnly = 1; + let Itinerary = TransALU; +} class LOG_CLAMPED_Common inst> : R600_1OP < inst, "LOG_CLAMPED", [] @@ -1325,50 +1342,84 @@ class LOG_CLAMPED_Common inst> : R600_1OP < class LOG_IEEE_Common inst> : R600_1OP_Helper < inst, "LOG_IEEE", flog2 ->; +> { + let TransOnly = 1; + let Itinerary = TransALU; +} class LSHL_Common inst> : R600_2OP_Helper ; class LSHR_Common inst> : R600_2OP_Helper ; class ASHR_Common inst> : R600_2OP_Helper ; class MULHI_INT_Common inst> : R600_2OP_Helper < inst, "MULHI_INT", mulhs ->; +> { + let TransOnly = 1; + let Itinerary = TransALU; +} class MULHI_UINT_Common inst> : R600_2OP_Helper < inst, "MULHI", mulhu ->; +> { + let TransOnly = 1; + let Itinerary = TransALU; +} class MULLO_INT_Common inst> : R600_2OP_Helper < inst, "MULLO_INT", mul ->; -class MULLO_UINT_Common inst> : R600_2OP ; +> { + let TransOnly = 1; + let Itinerary = TransALU; +} +class MULLO_UINT_Common inst> : R600_2OP { + let TransOnly = 1; + let Itinerary = TransALU; +} class RECIP_CLAMPED_Common inst> : R600_1OP < inst, "RECIP_CLAMPED", [] ->; +> { + let TransOnly = 1; + let Itinerary = TransALU; +} class RECIP_IEEE_Common inst> : R600_1OP < inst, "RECIP_IEEE", [(set R600_Reg32:$dst, (fdiv FP_ONE, R600_Reg32:$src0))] ->; +> { + let TransOnly = 1; + let Itinerary = TransALU; +} class RECIP_UINT_Common inst> : R600_1OP_Helper < inst, "RECIP_UINT", AMDGPUurecip ->; +> { + let TransOnly = 1; + let Itinerary = TransALU; +} class RECIPSQRT_CLAMPED_Common inst> : R600_1OP_Helper < inst, "RECIPSQRT_CLAMPED", int_AMDGPU_rsq ->; +> { + let TransOnly = 1; + let Itinerary = TransALU; +} class RECIPSQRT_IEEE_Common inst> : R600_1OP < inst, "RECIPSQRT_IEEE", [] ->; +> { + let TransOnly = 1; + let Itinerary = TransALU; +} class SIN_Common inst> : R600_1OP < inst, "SIN", []>{ let Trig = 1; + let TransOnly = 1; + let Itinerary = TransALU; } class COS_Common inst> : R600_1OP < inst, "COS", []> { let Trig = 1; + let TransOnly = 1; + let Itinerary = TransALU; } //===----------------------------------------------------------------------===// diff --git a/lib/Target/R600/R600Schedule.td b/lib/Target/R600/R600Schedule.td index 7ede181c51d..78a460ae9d7 100644 --- a/lib/Target/R600/R600Schedule.td +++ b/lib/Target/R600/R600Schedule.td @@ -24,7 +24,7 @@ def AnyALU : InstrItinClass; def VecALU : InstrItinClass; def TransALU : InstrItinClass; -def R600_EG_Itin : ProcessorItineraries < +def R600_VLIW5_Itin : ProcessorItineraries < [ALU_X, ALU_Y, ALU_Z, ALU_W, TRANS, ALU_NULL], [], [ @@ -34,3 +34,14 @@ def R600_EG_Itin : ProcessorItineraries < InstrItinData]> ] >; + +def R600_VLIW4_Itin : ProcessorItineraries < + [ALU_X, ALU_Y, ALU_Z, ALU_W, ALU_NULL], + [], + [ + InstrItinData]>, + InstrItinData]>, + InstrItinData]>, + InstrItinData]> + ] +>;