6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-02-05 14:34:55 +00:00
Code Issues Projects Releases Wiki Activity

Store CodeGenRegisters as pointers so they won't be reallocated.

Browse Source 
Reuse the CodeGenRegBank DenseMap in a few places that would build their
own or use linear search.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133333 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen 2011-06-18 04:26:06 +00:00
parent 54c47c1ce9
commit abdbc84b4e
9 changed files with 50 additions and 71 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

19
utils/TableGen/AsmMatcherEmitter.cpp
View File

@ -886,7 +886,8 @@ AsmMatcherInfo::getOperandClass(const CGIOperandList::OperandInfo &OI,
void AsmMatcherInfo::
BuildRegisterClasses(SmallPtrSet<Record*, 16> &SingletonRegisters) {
const std::vector<CodeGenRegister> &Registers = Target.getRegisters();
const std::vector<CodeGenRegister*> &Registers =
Target.getRegBank().getRegisters();
const std::vector<CodeGenRegisterClass> &RegClassList =
Target.getRegisterClasses();
@ -910,9 +911,9 @@ BuildRegisterClasses(SmallPtrSet<Record*, 16> &SingletonRegisters) {
// a unique register set class), and build the mapping of registers to the set
// they should classify to.
std::map<Record*, std::set<Record*> > RegisterMap;
for (std::vector<CodeGenRegister>::const_iterator it = Registers.begin(),
for (std::vector<CodeGenRegister*>::const_iterator it = Registers.begin(),
ie = Registers.end(); it != ie; ++it) {
const CodeGenRegister &CGR = *it;
const CodeGenRegister &CGR = **it;
// Compute the intersection of all sets containing this register.
std::set<Record*> ContainingSet;
@ -1745,14 +1746,16 @@ static void EmitMatchRegisterName(CodeGenTarget &Target, Record *AsmParser,
raw_ostream &OS) {
// Construct the match list.
std::vector<StringMatcher::StringPair> Matches;
for (unsigned i = 0, e = Target.getRegisters().size(); i != e; ++i) {
const CodeGenRegister &Reg = Target.getRegisters()[i];
if (Reg.TheDef->getValueAsString("AsmName").empty())
const std::vector<CodeGenRegister*> &Regs =
Target.getRegBank().getRegisters();
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
const CodeGenRegister *Reg = Regs[i];
if (Reg->TheDef->getValueAsString("AsmName").empty())
continue;
Matches.push_back(StringMatcher::StringPair(
Reg.TheDef->getValueAsString("AsmName"),
"return " + utostr(i + 1) + ";"));
Reg->TheDef->getValueAsString("AsmName"),
"return " + utostr(Reg->EnumValue) + ";"));
}
OS << "static unsigned MatchRegisterName(StringRef Name) {\n";

5
utils/TableGen/AsmWriterEmitter.cpp
View File

@ -462,7 +462,8 @@ void AsmWriterEmitter::EmitGetRegisterName(raw_ostream &O) {
CodeGenTarget Target(Records);
Record *AsmWriter = Target.getAsmWriter();
std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName");
const std::vector<CodeGenRegister> &Registers = Target.getRegisters();
const std::vector<CodeGenRegister*> &Registers =
Target.getRegBank().getRegisters();
StringToOffsetTable StringTable;
O <<
@ -476,7 +477,7 @@ void AsmWriterEmitter::EmitGetRegisterName(raw_ostream &O) {
<< "\n"
<< " static const unsigned RegAsmOffset[] = {";
for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
const CodeGenRegister &Reg = Registers[i];
const CodeGenRegister &Reg = *Registers[i];
std::string AsmName = Reg.TheDef->getValueAsString("AsmName");
if (AsmName.empty())

22
utils/TableGen/CodeGenRegisters.cpp
View File

@ -272,7 +272,7 @@ CodeGenRegBank::CodeGenRegBank(RecordKeeper &Records) : Records(Records) {
Registers.reserve(Regs.size());
// Assign the enumeration values.
for (unsigned i = 0, e = Regs.size(); i != e; ++i)
Registers.push_back(CodeGenRegister(Regs[i], i + 1));
getReg(Regs[i]);
// Read in register class definitions.
std::vector<Record*> RCs = Records.getAllDerivedDefinitions("RegisterClass");
@ -285,14 +285,12 @@ CodeGenRegBank::CodeGenRegBank(RecordKeeper &Records) : Records(Records) {
}
CodeGenRegister *CodeGenRegBank::getReg(Record *Def) {
if (Def2Reg.empty())
for (unsigned i = 0, e = Registers.size(); i != e; ++i)
Def2Reg[Registers[i].TheDef] = &Registers[i];
if (CodeGenRegister *Reg = Def2Reg[Def])
CodeGenRegister *&Reg = Def2Reg[Def];
if (Reg)
return Reg;
throw TGError(Def->getLoc(), "Not a known Register!");
Reg = new CodeGenRegister(Def, Registers.size() + 1);
Registers.push_back(Reg);
return Reg;
}
CodeGenRegisterClass *CodeGenRegBank::getRegClass(Record *Def) {
@ -332,10 +330,10 @@ void CodeGenRegBank::computeComposites() {
// Precompute all sub-register maps. This will create Composite entries for
// all inferred sub-register indices.
for (unsigned i = 0, e = Registers.size(); i != e; ++i)
Registers[i].getSubRegs(*this);
Registers[i]->getSubRegs(*this);
for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
CodeGenRegister *Reg1 = &Registers[i];
CodeGenRegister *Reg1 = Registers[i];
const CodeGenRegister::SubRegMap &SRM1 = Reg1->getSubRegs();
for (CodeGenRegister::SubRegMap::const_iterator i1 = SRM1.begin(),
e1 = SRM1.end(); i1 != e1; ++i1) {
@ -421,7 +419,7 @@ computeOverlaps(std::map<const CodeGenRegister*, CodeGenRegister::Set> &Map) {
// Collect overlaps that don't follow from rule 2.
for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
CodeGenRegister *Reg = &Registers[i];
CodeGenRegister *Reg = Registers[i];
CodeGenRegister::Set &Overlaps = Map[Reg];
// Reg overlaps itself.
@ -447,7 +445,7 @@ computeOverlaps(std::map<const CodeGenRegister*, CodeGenRegister::Set> &Map) {
// Apply rule 2. and inherit all sub-register overlaps.
for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
CodeGenRegister *Reg = &Registers[i];
CodeGenRegister *Reg = Registers[i];
CodeGenRegister::Set &Overlaps = Map[Reg];
const CodeGenRegister::SubRegMap &SRM = Reg->getSubRegs();
for (CodeGenRegister::SubRegMap::const_iterator i2 = SRM.begin(),

4
utils/TableGen/CodeGenRegisters.h
View File

@ -148,7 +148,7 @@ namespace llvm {
std::vector<Record*> SubRegIndices;
unsigned NumNamedIndices;
std::vector<CodeGenRegister> Registers;
std::vector<CodeGenRegister*> Registers;
DenseMap<Record*, CodeGenRegister*> Def2Reg;
std::vector<CodeGenRegisterClass> RegClasses;
@ -179,7 +179,7 @@ namespace llvm {
// Find or create a sub-register index representing the A+B composition.
Record *getCompositeSubRegIndex(Record *A, Record *B, bool create = false);
const std::vector<CodeGenRegister> &getRegisters() { return Registers; }
const std::vector<CodeGenRegister*> &getRegisters() { return Registers; }
// Find a register from its Record def.
CodeGenRegister *getReg(Record*);

10
utils/TableGen/CodeGenTarget.cpp
View File

@ -167,12 +167,10 @@ CodeGenRegBank &CodeGenTarget::getRegBank() const {
/// getRegisterByName - If there is a register with the specific AsmName,
/// return it.
const CodeGenRegister *CodeGenTarget::getRegisterByName(StringRef Name) const {
const std::vector<CodeGenRegister> &Regs = getRegBank().getRegisters();
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
const CodeGenRegister &Reg = Regs[i];
if (Reg.TheDef->getValueAsString("AsmName") == Name)
return &Reg;
}
const std::vector<CodeGenRegister*> &Regs = getRegBank().getRegisters();
for (unsigned i = 0, e = Regs.size(); i != e; ++i)
if (Regs[i]->TheDef->getValueAsString("AsmName") == Name)
return Regs[i];
return 0;
}

4
utils/TableGen/CodeGenTarget.h
View File

@ -96,10 +96,6 @@ public:
/// getRegBank - Return the register bank description.
CodeGenRegBank &getRegBank() const;
const std::vector<CodeGenRegister> &getRegisters() const {
return getRegBank().getRegisters();
}
/// getRegisterByName - If there is a register with the specific AsmName,
/// return it.
const CodeGenRegister *getRegisterByName(StringRef Name) const;

15
utils/TableGen/DAGISelMatcherGen.cpp
View File

@ -93,10 +93,6 @@ namespace {
/// CurPredicate - As we emit matcher nodes, this points to the latest check
/// which should have future checks stuck into its Next position.
Matcher *CurPredicate;
/// RegisterDefMap - A map of register record definitions to the
/// corresponding target CodeGenRegister entry.
DenseMap<const Record *, const CodeGenRegister *> RegisterDefMap;
public:
MatcherGen(const PatternToMatch &pattern, const CodeGenDAGPatterns &cgp);
@ -165,12 +161,6 @@ MatcherGen::MatcherGen(const PatternToMatch &pattern,
// If there are types that are manifestly known, infer them.
InferPossibleTypes();
// Populate the map from records to CodeGenRegister entries.
const CodeGenTarget &CGT = CGP.getTargetInfo();
const std::vector<CodeGenRegister> &Registers = CGT.getRegisters();
for (unsigned i = 0, e = Registers.size(); i != e; ++i)
RegisterDefMap[Registers[i].TheDef] = &Registers[i];
}
/// InferPossibleTypes - As we emit the pattern, we end up generating type
@ -590,8 +580,9 @@ void MatcherGen::EmitResultLeafAsOperand(const TreePatternNode *N,
// If this is an explicit register reference, handle it.
if (DefInit *DI = dynamic_cast<DefInit*>(N->getLeafValue())) {
if (DI->getDef()->isSubClassOf("Register")) {
AddMatcher(new EmitRegisterMatcher(RegisterDefMap[DI->getDef()],
N->getType(0)));
const CodeGenRegister *Reg =
CGP.getTargetInfo().getRegBank().getReg(DI->getDef());
AddMatcher(new EmitRegisterMatcher(Reg, N->getType(0)));
ResultOps.push_back(NextRecordedOperandNo++);
return;
}

10
utils/TableGen/FastISelEmitter.cpp
View File

@ -406,15 +406,7 @@ static std::string PhyRegForNode(TreePatternNode *Op,
PhysReg += static_cast<StringInit*>(OpLeafRec->getValue( \
"Namespace")->getValue())->getValue();
PhysReg += "::";
std::vector<CodeGenRegister> Regs = Target.getRegisters();
for (unsigned i = 0; i < Regs.size(); ++i) {
if (Regs[i].TheDef == OpLeafRec) {
PhysReg += Regs[i].getName();
break;
}
}
PhysReg += Target.getRegBank().getReg(OpLeafRec)->getName();
return PhysReg;
}

32
utils/TableGen/RegisterInfoEmitter.cpp
View File

@ -28,9 +28,9 @@ using namespace llvm;
void RegisterInfoEmitter::runEnums(raw_ostream &OS) {
CodeGenTarget Target(Records);
CodeGenRegBank &Bank = Target.getRegBank();
const std::vector<CodeGenRegister> &Registers = Target.getRegisters();
const std::vector<CodeGenRegister*> &Registers = Bank.getRegisters();
std::string Namespace = Registers[0].TheDef->getValueAsString("Namespace");
std::string Namespace = Registers[0]->TheDef->getValueAsString("Namespace");
EmitSourceFileHeader("Target Register Enum Values", OS);
OS << "namespace llvm {\n\n";
@ -40,9 +40,9 @@ void RegisterInfoEmitter::runEnums(raw_ostream &OS) {
OS << "enum {\n NoRegister,\n";
for (unsigned i = 0, e = Registers.size(); i != e; ++i)
OS << " " << Registers[i].getName() << " = " <<
Registers[i].EnumValue << ",\n";
assert(Registers.size() == Registers[Registers.size()-1].EnumValue &&
OS << " " << Registers[i]->getName() << " = " <<
Registers[i]->EnumValue << ",\n";
assert(Registers.size() == Registers[Registers.size()-1]->EnumValue &&
"Register enum value mismatch!");
OS << " NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n";
OS << "};\n";
@ -409,11 +409,11 @@ void RegisterInfoEmitter::run(raw_ostream &OS) {
typedef std::map<Record*, std::vector<int64_t>, LessRecord> DwarfRegNumsMapTy;
DwarfRegNumsMapTy DwarfRegNums;
const std::vector<CodeGenRegister> &Regs = Target.getRegisters();
const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters();
// Emit an overlap list for all registers.
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
const CodeGenRegister *Reg = &Regs[i];
const CodeGenRegister *Reg = Regs[i];
const CodeGenRegister::Set &O = Overlaps[Reg];
// Move Reg to the front so TRI::getAliasSet can share the list.
OS << " const unsigned " << Reg->getName() << "_Overlaps[] = { "
@ -430,7 +430,7 @@ void RegisterInfoEmitter::run(raw_ostream &OS) {
// Loop over all of the registers which have sub-registers, emitting the
// sub-registers list to memory.
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
const CodeGenRegister &Reg = Regs[i];
const CodeGenRegister &Reg = *Regs[i];
if (Reg.getSubRegs().empty())
continue;
// getSubRegs() orders by SubRegIndex. We want a topological order.
@ -447,7 +447,7 @@ void RegisterInfoEmitter::run(raw_ostream &OS) {
// Loop over all of the registers which have super-registers, emitting the
// super-registers list to memory.
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
const CodeGenRegister &Reg = Regs[i];
const CodeGenRegister &Reg = *Regs[i];
const CodeGenRegister::SuperRegList &SR = Reg.getSuperRegs();
if (SR.empty())
continue;
@ -463,7 +463,7 @@ void RegisterInfoEmitter::run(raw_ostream &OS) {
// Now that register alias and sub-registers sets have been emitted, emit the
// register descriptors now.
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
const CodeGenRegister &Reg = Regs[i];
const CodeGenRegister &Reg = *Regs[i];
OS << " { \"";
OS << Reg.getName() << "\",\t" << Reg.getName() << "_Overlaps,\t";
if (!Reg.getSubRegs().empty())
@ -514,10 +514,10 @@ void RegisterInfoEmitter::run(raw_ostream &OS) {
<< " switch (RegNo) {\n"
<< " default:\n return 0;\n";
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
const CodeGenRegister::SubRegMap &SRM = Regs[i].getSubRegs();
const CodeGenRegister::SubRegMap &SRM = Regs[i]->getSubRegs();
if (SRM.empty())
continue;
OS << " case " << getQualifiedName(Regs[i].TheDef) << ":\n";
OS << " case " << getQualifiedName(Regs[i]->TheDef) << ":\n";
OS << " switch (Index) {\n";
OS << " default: return 0;\n";
for (CodeGenRegister::SubRegMap::const_iterator ii = SRM.begin(),
@ -535,10 +535,10 @@ void RegisterInfoEmitter::run(raw_ostream &OS) {
<< " switch (RegNo) {\n"
<< " default:\n return 0;\n";
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
const CodeGenRegister::SubRegMap &SRM = Regs[i].getSubRegs();
const CodeGenRegister::SubRegMap &SRM = Regs[i]->getSubRegs();
if (SRM.empty())
continue;
OS << " case " << getQualifiedName(Regs[i].TheDef) << ":\n";
OS << " case " << getQualifiedName(Regs[i]->TheDef) << ":\n";
for (CodeGenRegister::SubRegMap::const_iterator ii = SRM.begin(),
ie = SRM.end(); ii != ie; ++ii)
OS << " if (SubRegNo == " << getQualifiedName(ii->second->TheDef)
@ -587,7 +587,7 @@ void RegisterInfoEmitter::run(raw_ostream &OS) {
// First, just pull all provided information to the map
unsigned maxLength = 0;
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
Record *Reg = Regs[i].TheDef;
Record *Reg = Regs[i]->TheDef;
std::vector<int64_t> RegNums = Reg->getValueAsListOfInts("DwarfNumbers");
maxLength = std::max((size_t)maxLength, RegNums.size());
if (DwarfRegNums.count(Reg))
@ -630,7 +630,7 @@ void RegisterInfoEmitter::run(raw_ostream &OS) {
OS << " };\n}\n\n";
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
Record *Reg = Regs[i].TheDef;
Record *Reg = Regs[i]->TheDef;
const RecordVal *V = Reg->getValue("DwarfAlias");
if (!V || !V->getValue())
continue;