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Replace copyRegToReg with copyPhysReg for ARM.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108078 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen 2010-07-11 06:33:54 +00:00
parent 629d80742a
commit ac27366700
6 changed files with 83 additions and 145 deletions
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111
lib/Target/ARM/ARMBaseInstrInfo.cpp
View File

@ -693,85 +693,44 @@ ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
return 0;
}
bool
ARMBaseInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *DestRC,
const TargetRegisterClass *SrcRC,
DebugLoc DL) const {
// tGPR or tcGPR is used sometimes in ARM instructions that need to avoid
// using certain registers. Just treat them as GPR here.
if (DestRC == ARM::tGPRRegisterClass || DestRC == ARM::tcGPRRegisterClass)
DestRC = ARM::GPRRegisterClass;
if (SrcRC == ARM::tGPRRegisterClass || SrcRC == ARM::tcGPRRegisterClass)
SrcRC = ARM::GPRRegisterClass;
void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I, DebugLoc DL,
unsigned DestReg, unsigned SrcReg,
bool KillSrc) const {
bool GPRDest = ARM::GPRRegClass.contains(DestReg);
bool GPRSrc = ARM::GPRRegClass.contains(SrcReg);
if (DestRC == ARM::SPR_8RegisterClass)
DestRC = ARM::SPRRegisterClass;
if (SrcRC == ARM::SPR_8RegisterClass)
SrcRC = ARM::SPRRegisterClass;
// Allow DPR / DPR_VFP2 / DPR_8 cross-class copies.
if (DestRC == ARM::DPR_8RegisterClass)
DestRC = ARM::DPR_VFP2RegisterClass;
if (SrcRC == ARM::DPR_8RegisterClass)
SrcRC = ARM::DPR_VFP2RegisterClass;
// NEONMoveFixPass will convert VFP moves to NEON moves when profitable.
if (DestRC == ARM::DPR_VFP2RegisterClass)
DestRC = ARM::DPRRegisterClass;
if (SrcRC == ARM::DPR_VFP2RegisterClass)
SrcRC = ARM::DPRRegisterClass;
// Allow QPR / QPR_VFP2 / QPR_8 cross-class copies.
if (DestRC == ARM::QPR_VFP2RegisterClass ||
DestRC == ARM::QPR_8RegisterClass)
DestRC = ARM::QPRRegisterClass;
if (SrcRC == ARM::QPR_VFP2RegisterClass ||
SrcRC == ARM::QPR_8RegisterClass)
SrcRC = ARM::QPRRegisterClass;
// Allow QQPR / QQPR_VFP2 cross-class copies.
if (DestRC == ARM::QQPR_VFP2RegisterClass)
DestRC = ARM::QQPRRegisterClass;
if (SrcRC == ARM::QQPR_VFP2RegisterClass)
SrcRC = ARM::QQPRRegisterClass;
// Disallow copies of unequal sizes.
if (DestRC != SrcRC && DestRC->getSize() != SrcRC->getSize())
return false;
if (DestRC == ARM::GPRRegisterClass) {
if (SrcRC == ARM::SPRRegisterClass)
AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VMOVRS), DestReg)
.addReg(SrcReg));
else
AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr),
DestReg).addReg(SrcReg)));
} else {
unsigned Opc;
if (DestRC == ARM::SPRRegisterClass)
Opc = (SrcRC == ARM::GPRRegisterClass ? ARM::VMOVSR : ARM::VMOVS);
else if (DestRC == ARM::DPRRegisterClass)
Opc = ARM::VMOVD;
else if (DestRC == ARM::QPRRegisterClass)
Opc = ARM::VMOVQ;
else if (DestRC == ARM::QQPRRegisterClass)
Opc = ARM::VMOVQQ;
else if (DestRC == ARM::QQQQPRRegisterClass)
Opc = ARM::VMOVQQQQ;
else
return false;
MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg);
MIB.addReg(SrcReg);
if (Opc != ARM::VMOVQQ && Opc != ARM::VMOVQQQQ)
AddDefaultPred(MIB);
if (GPRDest && GPRSrc) {
AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg)
.addReg(SrcReg, getKillRegState(KillSrc))));
return;
}
return true;
bool SPRDest = ARM::SPRRegClass.contains(DestReg);
bool SPRSrc = ARM::SPRRegClass.contains(SrcReg);
unsigned Opc;
if (SPRDest && SPRSrc)
Opc = ARM::VMOVS;
else if (GPRDest && SPRSrc)
Opc = ARM::VMOVRS;
else if (SPRDest && GPRSrc)
Opc = ARM::VMOVSR;
else if (ARM::DPRRegClass.contains(DestReg, SrcReg))
Opc = ARM::VMOVD;
else if (ARM::QPRRegClass.contains(DestReg, SrcReg))
Opc = ARM::VMOVQ;
else if (ARM::QQPRRegClass.contains(DestReg, SrcReg))
Opc = ARM::VMOVQQ;
else if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg))
Opc = ARM::VMOVQQQQ;
else
llvm_unreachable("Impossible reg-to-reg copy");
MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg);
MIB.addReg(SrcReg, getKillRegState(KillSrc));
if (Opc != ARM::VMOVQQ && Opc != ARM::VMOVQQQQ)
AddDefaultPred(MIB);
}
static const

10
lib/Target/ARM/ARMBaseInstrInfo.h
View File

@ -273,12 +273,10 @@ public:
virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
int &FrameIndex) const;
virtual bool copyRegToReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *DestRC,
const TargetRegisterClass *SrcRC,
DebugLoc DL) const;
virtual void copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I, DebugLoc DL,
unsigned DestReg, unsigned SrcReg,
bool KillSrc) const;
virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,

41
lib/Target/ARM/Thumb1InstrInfo.cpp
View File

@ -33,31 +33,24 @@ unsigned Thumb1InstrInfo::getUnindexedOpcode(unsigned Opc) const {
return 0;
}
bool Thumb1InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *DestRC,
const TargetRegisterClass *SrcRC,
DebugLoc DL) const {
if (DestRC == ARM::GPRRegisterClass || DestRC == ARM::tcGPRRegisterClass) {
if (SrcRC == ARM::GPRRegisterClass || SrcRC == ARM::tcGPRRegisterClass) {
BuildMI(MBB, I, DL, get(ARM::tMOVgpr2gpr), DestReg).addReg(SrcReg);
return true;
} else if (SrcRC == ARM::tGPRRegisterClass) {
BuildMI(MBB, I, DL, get(ARM::tMOVtgpr2gpr), DestReg).addReg(SrcReg);
return true;
}
} else if (DestRC == ARM::tGPRRegisterClass) {
if (SrcRC == ARM::GPRRegisterClass || SrcRC == ARM::tcGPRRegisterClass) {
BuildMI(MBB, I, DL, get(ARM::tMOVgpr2tgpr), DestReg).addReg(SrcReg);
return true;
} else if (SrcRC == ARM::tGPRRegisterClass) {
BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg).addReg(SrcReg);
return true;
}
}
void Thumb1InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I, DebugLoc DL,
unsigned DestReg, unsigned SrcReg,
bool KillSrc) const {
bool tDest = ARM::tGPRRegClass.contains(DestReg);
bool tSrc = ARM::tGPRRegClass.contains(SrcReg);
unsigned Opc = ARM::tMOVgpr2gpr;
if (tDest && tSrc)
Opc = ARM::tMOVr;
else if (tSrc)
Opc = ARM::tMOVtgpr2gpr;
else if (tDest)
Opc = ARM::tMOVgpr2tgpr;
return false;
BuildMI(MBB, I, DL, get(Opc), DestReg)
.addReg(SrcReg, getKillRegState(KillSrc));
assert(ARM::GPRRegClass.contains(DestReg, SrcReg) &&
"Thumb1 can only copy GPR registers");
}
bool Thumb1InstrInfo::

10
lib/Target/ARM/Thumb1InstrInfo.h
View File

@ -46,12 +46,10 @@ public:
const std::vector<CalleeSavedInfo> &CSI,
const TargetRegisterInfo *TRI) const;
bool copyRegToReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *DestRC,
const TargetRegisterClass *SrcRC,
DebugLoc DL) const;
void copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I, DebugLoc DL,
unsigned DestReg, unsigned SrcReg,
bool KillSrc) const;
void storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,
unsigned SrcReg, bool isKill, int FrameIndex,

46
lib/Target/ARM/Thumb2InstrInfo.cpp
View File

@ -120,34 +120,26 @@ isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumT,
NumT <= (IfCvtDiamondLimit) && NumF <= (IfCvtDiamondLimit);
}
bool
Thumb2InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *DestRC,
const TargetRegisterClass *SrcRC,
DebugLoc DL) const {
if (DestRC == ARM::GPRRegisterClass || DestRC == ARM::tcGPRRegisterClass) {
if (SrcRC == ARM::GPRRegisterClass || SrcRC == ARM::tcGPRRegisterClass) {
BuildMI(MBB, I, DL, get(ARM::tMOVgpr2gpr), DestReg).addReg(SrcReg);
return true;
} else if (SrcRC == ARM::tGPRRegisterClass) {
BuildMI(MBB, I, DL, get(ARM::tMOVtgpr2gpr), DestReg).addReg(SrcReg);
return true;
}
} else if (DestRC == ARM::tGPRRegisterClass) {
if (SrcRC == ARM::GPRRegisterClass || SrcRC == ARM::tcGPRRegisterClass) {
BuildMI(MBB, I, DL, get(ARM::tMOVgpr2tgpr), DestReg).addReg(SrcReg);
return true;
} else if (SrcRC == ARM::tGPRRegisterClass) {
BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg).addReg(SrcReg);
return true;
}
}
void Thumb2InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I, DebugLoc DL,
unsigned DestReg, unsigned SrcReg,
bool KillSrc) const {
// Handle SPR, DPR, and QPR copies.
return ARMBaseInstrInfo::copyRegToReg(MBB, I, DestReg, SrcReg, DestRC,
SrcRC, DL);
if (!ARM::GPRRegClass.contains(DestReg, SrcReg))
return ARMBaseInstrInfo::copyPhysReg(MBB, I, DL, DestReg, SrcReg, KillSrc);
bool tDest = ARM::tGPRRegClass.contains(DestReg);
bool tSrc = ARM::tGPRRegClass.contains(SrcReg);
unsigned Opc = ARM::tMOVgpr2gpr;
if (tDest && tSrc)
Opc = ARM::tMOVr;
else if (tSrc)
Opc = ARM::tMOVtgpr2gpr;
else if (tDest)
Opc = ARM::tMOVgpr2tgpr;
BuildMI(MBB, I, DL, get(Opc), DestReg)
.addReg(SrcReg, getKillRegState(KillSrc));
}
void Thumb2InstrInfo::

10
lib/Target/ARM/Thumb2InstrInfo.h
View File

@ -43,12 +43,10 @@ public:
bool isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumTInstrs,
MachineBasicBlock &FMBB, unsigned NumFInstrs) const;
bool copyRegToReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *DestRC,
const TargetRegisterClass *SrcRC,
DebugLoc DL) const;
void copyPhysReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I, DebugLoc DL,
unsigned DestReg, unsigned SrcReg,
bool KillSrc) const;
void storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI,