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[arm fast-isel] Appease the machine verifier by using the proper register

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classes.  Also a bit of cleanup.
rdar://12719844


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168728 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chad Rosier 2012-11-27 21:46:46 +00:00
parent 92a6e532b8
commit ac3158b571
1 changed files with 6 additions and 5 deletions
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11
lib/Target/ARM/ARMFastISel.cpp
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@ -1667,7 +1667,6 @@ bool ARMFastISel::SelectSelect(const Instruction *I) {
// Things need to be register sized for register moves.
if (VT != MVT::i32) return false;
const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
unsigned CondReg = getRegForValue(I->getOperand(0));
if (CondReg == 0) return false;
@ -1700,14 +1699,16 @@ bool ARMFastISel::SelectSelect(const Instruction *I) {
.addReg(CondReg).addImm(0));
unsigned MovCCOpc;
const TargetRegisterClass *RC;
if (!UseImm) {
RC = isThumb2 ? &ARM::tGPRRegClass : &ARM::GPRRegClass;
MovCCOpc = isThumb2 ? ARM::t2MOVCCr : ARM::MOVCCr;
} else {
if (!isNegativeImm) {
RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRRegClass;
if (!isNegativeImm)
MovCCOpc = isThumb2 ? ARM::t2MOVCCi : ARM::MOVCCi;
} else {
else
MovCCOpc = isThumb2 ? ARM::t2MVNCCi : ARM::MVNCCi;
}
}
unsigned ResultReg = createResultReg(RC);
if (!UseImm)
@ -2589,7 +2590,7 @@ unsigned ARMFastISel::ARMEmitIntExt(EVT SrcVT, unsigned SrcReg, EVT DestVT,
Opc = isThumb2 ? ARM::t2UXTH : ARM::UXTH;
} else {
Opc = isThumb2 ? ARM::t2SXTH : ARM::SXTH;
RC = isThumb2 ?&ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass;
}
break;
case MVT::i8: