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Track IR ordering of SelectionDAG nodes 2/4.
Change SelectionDAG::getXXXNode() interfaces as well as call sites of these functions to pass in SDLoc instead of DebugLoc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182703 91177308-0d34-0410-b5e6-96231b3b80d8
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@@ -214,7 +214,7 @@ void MipsSEDAGToDAGISel::processFunctionAfterISel(MachineFunction &MF) {
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}
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SDNode *MipsSEDAGToDAGISel::selectAddESubE(unsigned MOp, SDValue InFlag,
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SDValue CmpLHS, DebugLoc DL,
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SDValue CmpLHS, SDLoc DL,
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SDNode *Node) const {
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unsigned Opc = InFlag.getOpcode(); (void)Opc;
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@@ -316,7 +316,7 @@ bool MipsSEDAGToDAGISel::selectIntAddr(SDValue Addr, SDValue &Base,
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std::pair<bool, SDNode*> MipsSEDAGToDAGISel::selectNode(SDNode *Node) {
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unsigned Opcode = Node->getOpcode();
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DebugLoc DL = Node->getDebugLoc();
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SDLoc DL(Node);
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///
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// Instruction Selection not handled by the auto-generated
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@@ -374,7 +374,7 @@ std::pair<bool, SDNode*> MipsSEDAGToDAGISel::selectNode(SDNode *Node) {
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AnalyzeImm.Analyze(Imm, Size, false);
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MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin();
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DebugLoc DL = CN->getDebugLoc();
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SDLoc DL(CN);
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SDNode *RegOpnd;
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SDValue ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd),
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MVT::i64);
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@@ -416,7 +416,7 @@ std::pair<bool, SDNode*> MipsSEDAGToDAGISel::selectNode(SDNode *Node) {
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}
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SDNode *Rdhwr =
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CurDAG->getMachineNode(RdhwrOpc, Node->getDebugLoc(),
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CurDAG->getMachineNode(RdhwrOpc, SDLoc(Node),
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Node->getValueType(0),
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CurDAG->getRegister(SrcReg, PtrVT));
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SDValue Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), DL, DestReg,
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