mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-11-08 03:18:19 +00:00
Add support for generating reg+reg preinc stores on PPC.
PPC will now generate STWUX and friends. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158698 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
@@ -328,14 +328,14 @@ void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II,
|
||||
// address of new allocated space.
|
||||
if (LP64) {
|
||||
if (requiresRegisterScavenging(MF)) // FIXME (64-bit): Use "true" part.
|
||||
BuildMI(MBB, II, dl, TII.get(PPC::STDUX))
|
||||
BuildMI(MBB, II, dl, TII.get(PPC::STDUX), PPC::X1)
|
||||
.addReg(Reg, RegState::Kill)
|
||||
.addReg(PPC::X1, RegState::Define)
|
||||
.addReg(PPC::X1)
|
||||
.addReg(MI.getOperand(1).getReg());
|
||||
else
|
||||
BuildMI(MBB, II, dl, TII.get(PPC::STDUX))
|
||||
BuildMI(MBB, II, dl, TII.get(PPC::STDUX), PPC::X1)
|
||||
.addReg(PPC::X0, RegState::Kill)
|
||||
.addReg(PPC::X1, RegState::Define)
|
||||
.addReg(PPC::X1)
|
||||
.addReg(MI.getOperand(1).getReg());
|
||||
|
||||
if (!MI.getOperand(1).isKill())
|
||||
@@ -349,9 +349,9 @@ void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II,
|
||||
.addImm(maxCallFrameSize)
|
||||
.addReg(MI.getOperand(1).getReg(), RegState::ImplicitKill);
|
||||
} else {
|
||||
BuildMI(MBB, II, dl, TII.get(PPC::STWUX))
|
||||
BuildMI(MBB, II, dl, TII.get(PPC::STWUX), PPC::R1)
|
||||
.addReg(Reg, RegState::Kill)
|
||||
.addReg(PPC::R1, RegState::Define)
|
||||
.addReg(PPC::R1)
|
||||
.addReg(MI.getOperand(1).getReg());
|
||||
|
||||
if (!MI.getOperand(1).isKill())
|
||||
|
||||
Reference in New Issue
Block a user