mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-04-14 22:38:03 +00:00
Refactor code a bit to reduce number of calls in the final compiled code. No functional change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162166 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper
parent
8188955b2b
commit
acaaa6fae6
@ -12919,167 +12919,177 @@ X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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return EmitMonitor(MI, BB);
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// Atomic Lowering.
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case X86::ATOMAND32:
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return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
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X86::AND32ri, X86::MOV32rm,
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X86::LCMPXCHG32,
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X86::NOT32r, X86::EAX,
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&X86::GR32RegClass);
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case X86::ATOMOR32:
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return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr,
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X86::OR32ri, X86::MOV32rm,
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X86::LCMPXCHG32,
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X86::NOT32r, X86::EAX,
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&X86::GR32RegClass);
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case X86::ATOMXOR32:
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return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr,
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X86::XOR32ri, X86::MOV32rm,
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X86::LCMPXCHG32,
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X86::NOT32r, X86::EAX,
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&X86::GR32RegClass);
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case X86::ATOMNAND32:
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return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr,
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X86::AND32ri, X86::MOV32rm,
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X86::LCMPXCHG32,
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X86::NOT32r, X86::EAX,
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&X86::GR32RegClass, true);
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case X86::ATOMMIN32:
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return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr);
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case X86::ATOMMAX32:
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return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr);
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case X86::ATOMUMIN32:
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return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr);
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case X86::ATOMUMAX32:
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return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr);
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case X86::ATOMMIN16:
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case X86::ATOMMAX16:
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case X86::ATOMUMIN16:
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case X86::ATOMUMAX16:
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case X86::ATOMMIN64:
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case X86::ATOMMAX64:
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case X86::ATOMUMIN64:
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case X86::ATOMUMAX64: {
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unsigned Opc;
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switch (MI->getOpcode()) {
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default: llvm_unreachable("illegal opcode!");
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case X86::ATOMMIN32: Opc = X86::CMOVL32rr; break;
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case X86::ATOMMAX32: Opc = X86::CMOVG32rr; break;
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case X86::ATOMUMIN32: Opc = X86::CMOVB32rr; break;
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case X86::ATOMUMAX32: Opc = X86::CMOVA32rr; break;
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case X86::ATOMMIN16: Opc = X86::CMOVL16rr; break;
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case X86::ATOMMAX16: Opc = X86::CMOVG16rr; break;
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case X86::ATOMUMIN16: Opc = X86::CMOVB16rr; break;
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case X86::ATOMUMAX16: Opc = X86::CMOVA16rr; break;
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case X86::ATOMMIN64: Opc = X86::CMOVL64rr; break;
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case X86::ATOMMAX64: Opc = X86::CMOVG64rr; break;
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case X86::ATOMUMIN64: Opc = X86::CMOVB64rr; break;
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case X86::ATOMUMAX64: Opc = X86::CMOVA64rr; break;
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// FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
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}
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return EmitAtomicMinMaxWithCustomInserter(MI, BB, Opc);
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}
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case X86::ATOMAND32:
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case X86::ATOMOR32:
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case X86::ATOMXOR32:
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case X86::ATOMNAND32: {
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bool Invert = false;
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unsigned RegOpc, ImmOpc;
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switch (MI->getOpcode()) {
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default: llvm_unreachable("illegal opcode!");
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case X86::ATOMAND32:
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RegOpc = X86::AND32rr; ImmOpc = X86::AND32ri; break;
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case X86::ATOMOR32:
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RegOpc = X86::OR32rr; ImmOpc = X86::OR32ri; break;
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case X86::ATOMXOR32:
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RegOpc = X86::XOR32rr; ImmOpc = X86::XOR32ri; break;
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case X86::ATOMNAND32:
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RegOpc = X86::AND32rr; ImmOpc = X86::AND32ri; Invert = true; break;
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}
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return EmitAtomicBitwiseWithCustomInserter(MI, BB, RegOpc, ImmOpc,
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X86::MOV32rm, X86::LCMPXCHG32,
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X86::NOT32r, X86::EAX,
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&X86::GR32RegClass, Invert);
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}
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case X86::ATOMAND16:
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return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
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X86::AND16ri, X86::MOV16rm,
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X86::LCMPXCHG16,
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X86::NOT16r, X86::AX,
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&X86::GR16RegClass);
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case X86::ATOMOR16:
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return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr,
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X86::OR16ri, X86::MOV16rm,
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X86::LCMPXCHG16,
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X86::NOT16r, X86::AX,
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&X86::GR16RegClass);
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case X86::ATOMXOR16:
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return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr,
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X86::XOR16ri, X86::MOV16rm,
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X86::LCMPXCHG16,
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case X86::ATOMNAND16: {
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bool Invert = false;
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unsigned RegOpc, ImmOpc;
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switch (MI->getOpcode()) {
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default: llvm_unreachable("illegal opcode!");
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case X86::ATOMAND16:
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RegOpc = X86::AND16rr; ImmOpc = X86::AND16ri; break;
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case X86::ATOMOR16:
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RegOpc = X86::OR16rr; ImmOpc = X86::OR16ri; break;
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case X86::ATOMXOR16:
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RegOpc = X86::XOR16rr; ImmOpc = X86::XOR16ri; break;
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case X86::ATOMNAND16:
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RegOpc = X86::AND16rr; ImmOpc = X86::AND16ri; Invert = true; break;
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}
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return EmitAtomicBitwiseWithCustomInserter(MI, BB, RegOpc, ImmOpc,
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X86::MOV16rm, X86::LCMPXCHG16,
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X86::NOT16r, X86::AX,
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&X86::GR16RegClass);
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case X86::ATOMNAND16:
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return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr,
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X86::AND16ri, X86::MOV16rm,
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X86::LCMPXCHG16,
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X86::NOT16r, X86::AX,
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&X86::GR16RegClass, true);
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case X86::ATOMMIN16:
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return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr);
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case X86::ATOMMAX16:
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return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr);
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case X86::ATOMUMIN16:
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return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr);
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case X86::ATOMUMAX16:
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return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr);
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&X86::GR16RegClass, Invert);
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}
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case X86::ATOMAND8:
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return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
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X86::AND8ri, X86::MOV8rm,
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X86::LCMPXCHG8,
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X86::NOT8r, X86::AL,
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&X86::GR8RegClass);
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case X86::ATOMOR8:
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return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr,
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X86::OR8ri, X86::MOV8rm,
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X86::LCMPXCHG8,
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X86::NOT8r, X86::AL,
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&X86::GR8RegClass);
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case X86::ATOMXOR8:
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return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr,
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X86::XOR8ri, X86::MOV8rm,
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X86::LCMPXCHG8,
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case X86::ATOMNAND8: {
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bool Invert = false;
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unsigned RegOpc, ImmOpc;
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switch (MI->getOpcode()) {
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default: llvm_unreachable("illegal opcode!");
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case X86::ATOMAND8:
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RegOpc = X86::AND8rr; ImmOpc = X86::AND8ri; break;
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case X86::ATOMOR8:
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RegOpc = X86::OR8rr; ImmOpc = X86::OR8ri; break;
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case X86::ATOMXOR8:
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RegOpc = X86::XOR8rr; ImmOpc = X86::XOR8ri; break;
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case X86::ATOMNAND8:
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RegOpc = X86::AND8rr; ImmOpc = X86::AND8ri; Invert = true; break;
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}
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return EmitAtomicBitwiseWithCustomInserter(MI, BB, RegOpc, ImmOpc,
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X86::MOV8rm, X86::LCMPXCHG8,
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X86::NOT8r, X86::AL,
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&X86::GR8RegClass);
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case X86::ATOMNAND8:
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return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr,
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X86::AND8ri, X86::MOV8rm,
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X86::LCMPXCHG8,
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X86::NOT8r, X86::AL,
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&X86::GR8RegClass, true);
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// FIXME: There are no CMOV8 instructions; MIN/MAX need some other way.
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&X86::GR8RegClass, Invert);
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}
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// This group is for 64-bit host.
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case X86::ATOMAND64:
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return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
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X86::AND64ri32, X86::MOV64rm,
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X86::LCMPXCHG64,
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X86::NOT64r, X86::RAX,
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&X86::GR64RegClass);
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case X86::ATOMOR64:
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return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr,
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X86::OR64ri32, X86::MOV64rm,
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X86::LCMPXCHG64,
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X86::NOT64r, X86::RAX,
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&X86::GR64RegClass);
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case X86::ATOMXOR64:
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return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr,
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X86::XOR64ri32, X86::MOV64rm,
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X86::LCMPXCHG64,
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case X86::ATOMNAND64: {
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bool Invert = false;
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unsigned RegOpc, ImmOpc;
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switch (MI->getOpcode()) {
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default: llvm_unreachable("illegal opcode!");
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case X86::ATOMAND64:
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RegOpc = X86::AND64rr; ImmOpc = X86::AND64ri32; break;
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case X86::ATOMOR64:
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RegOpc = X86::OR64rr; ImmOpc = X86::OR64ri32; break;
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case X86::ATOMXOR64:
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RegOpc = X86::XOR64rr; ImmOpc = X86::XOR64ri32; break;
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case X86::ATOMNAND64:
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RegOpc = X86::AND64rr; ImmOpc = X86::AND64ri32; Invert = true; break;
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}
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return EmitAtomicBitwiseWithCustomInserter(MI, BB, RegOpc, ImmOpc,
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X86::MOV64rm, X86::LCMPXCHG64,
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X86::NOT64r, X86::RAX,
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&X86::GR64RegClass);
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case X86::ATOMNAND64:
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return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr,
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X86::AND64ri32, X86::MOV64rm,
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X86::LCMPXCHG64,
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X86::NOT64r, X86::RAX,
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&X86::GR64RegClass, true);
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case X86::ATOMMIN64:
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return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr);
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case X86::ATOMMAX64:
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return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr);
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case X86::ATOMUMIN64:
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return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr);
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case X86::ATOMUMAX64:
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return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr);
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&X86::GR64RegClass, Invert);
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}
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// This group does 64-bit operations on a 32-bit host.
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case X86::ATOMAND6432:
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return EmitAtomicBit6432WithCustomInserter(MI, BB,
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X86::AND32rr, X86::AND32rr,
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X86::AND32ri, X86::AND32ri,
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false);
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case X86::ATOMOR6432:
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return EmitAtomicBit6432WithCustomInserter(MI, BB,
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X86::OR32rr, X86::OR32rr,
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X86::OR32ri, X86::OR32ri,
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false);
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case X86::ATOMXOR6432:
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return EmitAtomicBit6432WithCustomInserter(MI, BB,
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X86::XOR32rr, X86::XOR32rr,
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X86::XOR32ri, X86::XOR32ri,
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false);
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case X86::ATOMNAND6432:
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return EmitAtomicBit6432WithCustomInserter(MI, BB,
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X86::AND32rr, X86::AND32rr,
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X86::AND32ri, X86::AND32ri,
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true);
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case X86::ATOMADD6432:
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return EmitAtomicBit6432WithCustomInserter(MI, BB,
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X86::ADD32rr, X86::ADC32rr,
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X86::ADD32ri, X86::ADC32ri,
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false);
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case X86::ATOMSUB6432:
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return EmitAtomicBit6432WithCustomInserter(MI, BB,
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X86::SUB32rr, X86::SBB32rr,
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X86::SUB32ri, X86::SBB32ri,
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false);
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case X86::ATOMSWAP6432:
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return EmitAtomicBit6432WithCustomInserter(MI, BB,
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X86::MOV32rr, X86::MOV32rr,
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X86::MOV32ri, X86::MOV32ri,
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false);
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case X86::ATOMSWAP6432: {
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bool Invert = false;
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unsigned RegOpcL, RegOpcH, ImmOpcL, ImmOpcH;
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switch (MI->getOpcode()) {
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default: llvm_unreachable("illegal opcode!");
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case X86::ATOMAND6432:
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RegOpcL = RegOpcH = X86::AND32rr;
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ImmOpcL = ImmOpcH = X86::AND32ri;
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break;
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case X86::ATOMOR6432:
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RegOpcL = RegOpcH = X86::OR32rr;
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ImmOpcL = ImmOpcH = X86::OR32ri;
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break;
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case X86::ATOMXOR6432:
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RegOpcL = RegOpcH = X86::XOR32rr;
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ImmOpcL = ImmOpcH = X86::XOR32ri;
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break;
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case X86::ATOMNAND6432:
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RegOpcL = RegOpcH = X86::AND32rr;
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ImmOpcL = ImmOpcH = X86::AND32ri;
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Invert = true;
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break;
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case X86::ATOMADD6432:
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RegOpcL = X86::ADD32rr; RegOpcH = X86::ADC32rr;
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ImmOpcL = X86::ADD32ri; ImmOpcH = X86::ADC32ri;
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break;
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case X86::ATOMSUB6432:
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RegOpcL = X86::SUB32rr; RegOpcH = X86::SBB32rr;
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ImmOpcL = X86::SUB32ri; ImmOpcH = X86::SBB32ri;
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break;
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case X86::ATOMSWAP6432:
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RegOpcL = RegOpcH = X86::MOV32rr;
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ImmOpcL = ImmOpcH = X86::MOV32ri;
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break;
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}
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return EmitAtomicBit6432WithCustomInserter(MI, BB, RegOpcL, RegOpcH,
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ImmOpcL, ImmOpcH, Invert);
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}
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case X86::VASTART_SAVE_XMM_REGS:
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return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB);
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