Make this readable for newbies and those who can only understand one set of

grammar rules for the English language.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21503 91177308-0d34-0410-b5e6-96231b3b80d8

docs/CodeGenerator.html

@@ -137,7 +137,7 @@ classes, ensuring that it is portable.
 code generator and the set of reusable components that can be used to build
 target-specific backends.  The two most important interfaces (<a
 href="#targetmachine"><tt>TargetMachine</tt></a> and <a
-href="#targetdata"><tt>TargetData</tt></a> classes) are the only ones that are
+href="#targetdata"><tt>TargetData</tt></a>) are the only ones that are
 required to be defined for a backend to fit into the LLVM system, but the others
 must be defined if the reusable code generator components are going to be
 used.</p>
@@ -188,30 +188,31 @@ set, then makes use of virtual registers in SSA form and physical registers that
 represent any required register assignments due to target constraints or calling
 conventions.</li>
 
-<li><b>SSA-based Machine Code Optimizations</b> - This (optional) stage consists
+<li><b><a href="#ssamco">SSA-based Machine Code Optimizations</a></b> - This 
-of a series of machine-code optimizations that operate on the SSA-form produced
+optional stage consists of a series of machine-code optimizations that 
-by the instruction selector.  Optimizations like modulo-scheduling, normal
+operate on the SSA-form produced by the instruction selector.  Optimizations 
-scheduling, or peephole optimization work here.</li>
+like modulo-scheduling, normal scheduling, or peephole optimization work here.
+</li>
 
-<li><b>Register Allocation</b> - The target code is transformed from an infinite
+<li><b><a name="#regalloc">Register Allocation</a></b> - The
-virtual register file in SSA form to the concrete register file used by the
+target code is transformed from an infinite virtual register file in SSA form 
-target.  This phase introduces spill code and eliminates all virtual register
+to the concrete register file used by the target.  This phase introduces spill 
-references from the program.</li>
+code and eliminates all virtual register references from the program.</li>
 
-<li><b>Prolog/Epilog Code Insertion</b> - Once the machine code has been
+<li><b><a name="#proepicode">Prolog/Epilog Code Insertion</a></b> - Once the 
-generated for the function and the amount of stack space required is known (used
+machine code has been generated for the function and the amount of stack space 
-for LLVM alloca's and spill slots), the prolog and epilog code for the function
+required is known (used for LLVM alloca's and spill slots), the prolog and 
-can be inserted and "abstract stack location references" can be eliminated.
+epilog code for the function can be inserted and "abstract stack location 
-This stage is responsible for implementing optimizations like frame-pointer
+references" can be eliminated.  This stage is responsible for implementing 
-elimination and stack packing.</li>
+optimizations like frame-pointer elimination and stack packing.</li>
 
-<li><b>Late Machine Code Optimizations</b> - Optimizations that operate on
+<li><b><a name="latemco">Late Machine Code Optimizations</a></b> - Optimizations
-"final" machine code can go here, such as spill code scheduling and peephole
+that operate on "final" machine code can go here, such as spill code scheduling
-optimizations.</li>
+and peephole optimizations.</li>
 
-<li><b>Code Emission</b> - The final stage actually outputs the code for
+<li><b><a name="codemission">Code Emission</a></b> - The final stage actually 
-the current function, either in the target assembler format or in machine
+puts out the code for the current function, either in the target assembler 
-code.</li>
+format or in machine code.</li>
 
 </ol>
 
@@ -245,11 +246,13 @@ targets with unusual requirements can be supported with custom passes as needed.
 
 <p>The target description classes require a detailed description of the target
 architecture.  These target descriptions often have a large amount of common
-information (e.g., an add instruction is almost identical to a sub instruction).
+information (e.g., an <tt>add</tt> instruction is almost identical to a 
+<tt>sub</tt> instruction).
 In order to allow the maximum amount of commonality to be factored out, the LLVM
 code generator uses the <a href="TableGenFundamentals.html">TableGen</a> tool to
-describe big chunks of the target machine, which allows the use of domain- and 
+describe big chunks of the target machine, which allows the use of
-target-specific abstractions to reduce the amount of repetition.
+domain-specific and target-specific abstractions to reduce the amount of 
+repetition.
 </p>
 
 </div>
@@ -264,11 +267,11 @@ target-specific abstractions to reduce the amount of repetition.
 
 <p>The LLVM target description classes (which are located in the
 <tt>include/llvm/Target</tt> directory) provide an abstract description of the
-target machine, independent of any particular client.  These classes are
+target machine; independent of any particular client.  These classes are
-designed to capture the <i>abstract</i> properties of the target (such as what
+designed to capture the <i>abstract</i> properties of the target (such as the
-instruction and registers it has), and do not incorporate any particular pieces
+instructions and registers it has), and do not incorporate any particular pieces
-of code generation algorithms (these interfaces do not take interference graphs
+of code generation algorithms. These interfaces do not take interference graphs
-as inputs or other algorithm-specific data structures).</p>
+as inputs or other algorithm-specific data structures.</p>
 
 <p>All of the target description classes (except the <tt><a
 href="#targetdata">TargetData</a></tt> class) are designed to be subclassed by
@@ -288,8 +291,9 @@ should be implemented by the target.</p>
 
 <p>The <tt>TargetMachine</tt> class provides virtual methods that are used to
 access the target-specific implementations of the various target description
-classes (with the <tt>getInstrInfo</tt>, <tt>getRegisterInfo</tt>,
+classes via the <tt>get*Info</tt> methods (<tt>getInstrInfo</tt>,
-<tt>getFrameInfo</tt>, ... methods).  This class is designed to be specialized by
+<tt>getRegisterInfo</tt>, <tt>getFrameInfo</tt>, etc.).  This class is 
+designed to be specialized by
 a concrete target implementation (e.g., <tt>X86TargetMachine</tt>) which
 implements the various virtual methods.  The only required target description
 class is the <a href="#targetdata"><tt>TargetData</tt></a> class, but if the
@@ -307,10 +311,11 @@ implemented as well.</p>
 <div class="doc_text">
 
 <p>The <tt>TargetData</tt> class is the only required target description class,
-and it is the only class that is not extensible (it cannot be derived from).  It
+and it is the only class that is not extensible. You cannot derived  a new 
-specifies information about how the target lays out memory for structures, the
+class from it.  <tt>TargetData</tt> specifies information about how the target 
-alignment requirements for various data types, the size of pointers in the
+lays out memory for structures, the alignment requirements for various data 
-target, and whether the target is little- or big-endian.</p>
+types, the size of pointers in the target, and whether the target is 
+little-endian or big-endian.</p>
 
 </div>
 
@@ -323,10 +328,12 @@ target, and whether the target is little- or big-endian.</p>
 
 <p>The <tt>TargetLowering</tt> class is used by SelectionDAG based instruction
 selectors primarily to describe how LLVM code should be lowered to SelectionDAG
-operations.  Among other things, this class indicates an initial register class
+operations.  Among other things, this class indicates:
-to use for various ValueTypes, which operations are natively supported by the
+<ul><li>an initial register class to use for various ValueTypes,</li>
-target machine, and some other miscellaneous properties (such as the return type
+  <li>which operations are natively supported by the target machine,</li>
-of setcc operations, the type to use for shift amounts, etc).</p>
+  <li>the return type of setcc operations, and</li>
+  <li>the type to use for shift amounts, etc</li>.
+</ol></p>
 
 </div>
 
@@ -415,12 +422,12 @@ representation for machine code, as well as a register allocated, non-SSA form.
 
 <p>Target machine instructions are represented as instances of the
 <tt>MachineInstr</tt> class.  This class is an extremely abstract way of
-representing machine instructions.  In particular, all it keeps track of is 
+representing machine instructions.  In particular, it only keeps track of 
-an opcode number and some number of operands.</p>
+an opcode number and a set of operands.</p>
 
-<p>The opcode number is an simple unsigned number that only has meaning to a 
+<p>The opcode number is a simple unsigned number that only has meaning to a 
 specific backend.  All of the instructions for a target should be defined in 
-the <tt>*InstrInfo.td</tt> file for the target, and the opcode enum values
+the <tt>*InstrInfo.td</tt> file for the target. The opcode enum values
 are auto-generated from this description.  The <tt>MachineInstr</tt> class does
 not have any information about how to interpret the instruction (i.e., what the 
 semantics of the instruction are): for that you must refer to the 
@@ -439,9 +446,9 @@ and stores the result into the "%i3" register.  In the LLVM code generator,
 the operands should be stored as "<tt>%i3, %i1, %i2</tt>": with the destination
 first.</p>
 
-<p>Keeping destination operands at the beginning of the operand list has several
+<p>Keeping destination (definition) operands at the beginning of the operand 
-advantages.  In particular, the debugging printer will print the instruction 
+list has several advantages.  In particular, the debugging printer will print 
-like this:</p>
+the instruction like this:</p>
 
 <pre>
   %r3 = add %i1, %i2
@@ -490,17 +497,18 @@ instructions.  Usage of the <tt>BuildMI</tt> functions look like this:
 
 <p>
 The key thing to remember with the <tt>BuildMI</tt> functions is that you have
-to specify the number of operands that the machine instruction will take 
+to specify the number of operands that the machine instruction will take. This
-(allowing efficient memory allocation).  Also, if operands default to be uses
+allows for efficient memory allocation.  You also need to specify if operands 
-of values, not definitions.  If you need to add a definition operand (other 
+default to be uses of values, not definitions.  If you need to add a definition
-than the optional destination register), you must explicitly mark it as such.
+operand (other than the optional destination register), you must explicitly 
+mark it as such.
 </p>
 
 </div>
 
 <!-- _______________________________________________________________________ -->
 <div class="doc_subsubsection">
-  <a name="fixedregs">Fixed (aka preassigned) registers</a>
+  <a name="fixedregs">Fixed (preassigned) registers</a>
 </div>
 
 <div class="doc_text">
@@ -509,7 +517,7 @@ than the optional destination register), you must explicitly mark it as such.
 presence of fixed registers.  In particular, there are often places in the 
 instruction stream where the register allocator <em>must</em> arrange for a
 particular value to be in a particular register.  This can occur due to 
-limitations in the instruction set (e.g., the X86 can only do a 32-bit divide 
+limitations of the instruction set (e.g., the X86 can only do a 32-bit divide 
 with the <tt>EAX</tt>/<tt>EDX</tt> registers), or external factors like calling
 conventions.  In any case, the instruction selector should emit code that 
 copies a virtual register into or out of a physical register when needed.</p>
@@ -570,7 +578,7 @@ register.</p>
 
 <div class="doc_text">
 
-<p><tt>MachineInstr</tt>'s are initially instruction selected in SSA-form, and
+<p><tt>MachineInstr</tt>'s are initially selected in SSA-form, and
 are maintained in SSA-form until register allocation happens.  For the most 
 part, this is trivially simple since LLVM is already in SSA form: LLVM PHI nodes
 become machine code PHI nodes, and virtual registers are only allowed to have a
@@ -602,7 +610,7 @@ explains how they work and some of the rationale behind their design.</p>
 
 <div class="doc_text">
 <p>
-Instruction Selection is the process of translating the LLVM code input to the
+Instruction Selection is the process of translating LLVM code presented to the
 code generator into target-specific machine instructions.  There are several
 well-known ways to do this in the literature.  In LLVM there are two main forms:
 the old-style 'simple' instruction selector (which effectively peephole selects
@@ -619,8 +627,9 @@ new port, we recommend that you write the instruction selector using the
 SelectionDAG infrastructure.</p>
 
 <p>In time, most of the target-specific code for instruction selection will be
-auto-generated from the target .td files.  For now, however, the <a
+auto-generated from the target description (<tt>*.td</tt>) files.  For now, 
-href="#selectiondag_select">Select Phase</a> must still be written by hand.</p>
+however, the <a href="#selectiondag_select">Select Phase</a> must still be 
+written by hand.</p>
 </div>
 
 <!-- _______________________________________________________________________ -->
@@ -631,39 +640,40 @@ href="#selectiondag_select">Select Phase</a> must still be written by hand.</p>
 <div class="doc_text">
 
 <p>
-The SelectionDAG provides an abstraction for representing code in a way that is
+The SelectionDAG provides an abstraction for code representation in a way that 
-amenable to instruction selection using automatic techniques
+is amenable to instruction selection using automatic techniques
-(e.g. dynamic-programming based optimal pattern matching selectors), as well as
+(e.g. dynamic-programming based optimal pattern matching selectors), It is also
-an abstraction that is useful for other phases of code generation (in
+well suited to other phases of code generation; in particular, instruction scheduling.  Additionally, the SelectionDAG provides a host representation where a 
-particular, instruction scheduling).  Additionally, the SelectionDAG provides a
+large variety of very-low-level (but target-independent) 
-host representation where a large variety of very-low-level (but
+<a href="#selectiondag_optimize">optimizations</a> may be
-target-independent) <a href="#selectiondag_optimize">optimizations</a> may be
 performed: ones which require extensive information about the instructions
 efficiently supported by the target.
 </p>
 
 <p>
 The SelectionDAG is a Directed-Acyclic-Graph whose nodes are instances of the
-<tt>SDNode</tt> class.  The primary payload of the Node is its operation code
+<tt>SDNode</tt> class.  The primary payload of the <tt>SDNode</tt> is its 
-(Opcode) that indicates what the operation the node performs.  The various
+operation code (Opcode) that indicates what operation the node performs.  
-operation node types are described at the top of the
+The various operation node types are described at the top of the
-<tt>include/llvm/CodeGen/SelectionDAGNodes.h</tt> file.  Depending on the operation, nodes may contain additional information (e.g. the condition code
+<tt>include/llvm/CodeGen/SelectionDAGNodes.h</tt> file.  Depending on the 
+operation, nodes may contain additional information (e.g. the condition code
 for a SETCC node) contained in a derived class.</p>
 
-<p>Each node in the graph may define multiple values
+<p>Although most operations define a single value, each node in the graph may 
-(e.g. for a combined div/rem operation and many other situations), though most
+define multiple values.  For example, a combined div/rem operation will define
-operations define a single value.  Each node also has some number of operands,
+both the dividend and the remainder. Many other situations require multiple
-which are edges to the node defining the used value.  Because nodes may define
+values as well.  Each node also has some number of operands, which are edges 
-multiple values, edges are represented by instances of the <tt>SDOperand</tt>
+to the node defining the used value.  Because nodes may define multiple values,
-class, which is a &lt;SDNode, unsigned&gt; pair, indicating the node and result
+edges are represented by instances of the <tt>SDOperand</tt> class, which is 
-value being used.  Each value produced by a SDNode has an associated
+a &lt;SDNode, unsigned&gt; pair, indicating the node and result
-MVT::ValueType, indicating what type the value is.
+value being used, respectively.  Each value produced by an SDNode has an 
+associated MVT::ValueType, indicating what type the value is.
 </p>
 
 <p>
-SelectionDAGs contain two different kinds of value: those that represent data
+SelectionDAGs contain two different kinds of values: those that represent data
 flow and those that represent control flow dependencies.  Data values are simple
-edges with a integer or floating point value type.  Control edges are
+edges with an integer or floating point value type.  Control edges are
 represented as "chain" edges which are of type MVT::Other.  These edges provide
 an ordering between nodes that have side effects (such as
 loads/stores/calls/return/etc).  All nodes that have side effects should take a
@@ -673,23 +683,23 @@ value produced by an operation.</p>
 
 <p>
 A SelectionDAG has designated "Entry" and "Root" nodes.  The Entry node is
-always a marker node with Opcode of ISD::TokenFactor.  The Root node is the
+always a marker node with an Opcode of ISD::TokenFactor.  The Root node is the
-final side effecting node in the token chain (for example, in a single basic
+final side-effecting node in the token chain. For example, in a single basic
-block function, this would be the return node).
+block function, this would be the return node.
 </p>
 
 <p>
-One important concept for SelectionDAGs is the notion of a "legal" vs "illegal"
+One important concept for SelectionDAGs is the notion of a "legal" vs. "illegal"
 DAG.  A legal DAG for a target is one that only uses supported operations and
 supported types.  On PowerPC, for example, a DAG with any values of i1, i8, i16,
 or i64 type would be illegal.  The <a href="#selectiondag_legalize">legalize</a>
-phase is the one responsible for turning an illegal DAG into a legal DAG.
+phase is responsible for turning an illegal DAG into a legal DAG.
 </p>
 </div>
 
 <!-- _______________________________________________________________________ -->
 <div class="doc_subsubsection">
-  <a name="selectiondag_process">SelectionDAG Code Generation Process</a>
+  <a name="selectiondag_process">SelectionDAG Instruction Selection Process</a>
 </div>
 
 <div class="doc_text">
@@ -706,7 +716,7 @@ SelectionDAG-based instruction selection consists of the following steps:
     performs simple optimizations on the SelectionDAG to simplify it and
     recognize meta instructions (like rotates and div/rem pairs) for
     targets that support these meta operations.  This makes the resultant code
-    more efficient and the 'select' phase more simple.
+    more efficient and the 'select instructions from DAG' phase (below) simpler.
 </li>
 <li><a href="#selectiondag_legalize">Legalize SelectionDAG</a> - This stage
     converts the illegal SelectionDAG to a legal SelectionDAG, by eliminating
@@ -734,11 +744,11 @@ rest of the code generation passes are run.</p>
 
 <p>
 The initial SelectionDAG is naively peephole expanded from the LLVM input by
-the SelectionDAGLowering class in the SelectionDAGISel.cpp file.  The idea of 
+the <tt>SelectionDAGLowering</tt> class in the SelectionDAGISel.cpp file.  The 
-doing this pass is to expose as much low-level target-specific details to the
+intent of  this pass is to expose as much low-level, target-specific details 
-SelectionDAG as possible.  This pass is mostly hard-coded (e.g. an LLVM add
+to the SelectionDAG as possible.  This pass is mostly hard-coded (e.g. an LLVM 
-turns into a SDNode add, a geteelementptr is expanded into the obvious
+add turns into an SDNode add while a geteelementptr is expanded into the obvious
-arithmetic, etc) but does require target-specific hooks to lower calls and
+arithmetic). This pass requires target-specific hooks to lower calls and
 returns, varargs, etc.  For these features, the TargetLowering interface is
 used.
 </p>
@@ -759,10 +769,11 @@ tasks:</p>
 <ol>
 <li><p>Convert values of unsupported types to values of supported types.</p>
     <p>There are two main ways of doing this: promoting a small type to a larger
-       type (e.g. f32 -> f64, or i16 -> i32), and expanding larger integer types
+       type (e.g. f32 -> f64, or i16 -> i32), and demoting larg integer types
        to smaller ones (e.g. implementing i64 with i32 operations where
-       possible).  Promotion insert sign and zero extensions as needed to make
+       possible).  Type conversions can insert sign and zero extensions as 
-       sure that the final code has the same behavior as the input.</p>
+       needed to make sure that the final code has the same behavior as the 
+       input.</p>
 </li>
 
 <li><p>Eliminate operations that are not supported by the target in a supported
@@ -772,19 +783,20 @@ tasks:</p>
        conditional moves).  Legalize takes care of either open-coding another 
        sequence of operations to emulate the operation (this is known as
        expansion), promoting to a larger type that supports the operation
-       (promotion), or can use a target-specific hook to implement the
+       (promotion), or using a target-specific hook to implement the
        legalization.</p>
 </li>
 </ol>
 
 <p>
 Instead of using a Legalize pass, we could require that every target-specific 
-<a href="#selectiondag_optimize">selector</a> support and expand every operator
+<a href="#selectiondag_optimize">selector</a> supports and expands every 
-and type even if they are not supported and may require many instructions to
+operator and type even if they are not supported and may require many 
-implement (in fact, this is the approach taken by the "simple" selectors).
+instructions to implement (in fact, this is the approach taken by the 
-However, using a Legalize pass allows all of the cannonicalization patterns to
+"simple" selectors).  However, using a Legalize pass allows all of the 
-be shared across targets, and makes it very easy to optimize the cannonicalized
+cannonicalization patterns to be shared across targets which makes it very 
-code (because it is still in the form of a DAG).
+easy to optimize the cannonicalized code because it is still in the form of 
+a DAG.
 </p>
 
 </div>
@@ -798,11 +810,12 @@ code (because it is still in the form of a DAG).
 
 <p>
 The SelectionDAG optimization phase is run twice for code generation: once
-immediately after the DAG is built and once after legalization.  The first pass
+immediately after the DAG is built and once after legalization.  The first run
-allows the initial code to be cleaned up, (for example) performing optimizations
+of the pass allows the initial code to be cleaned up (e.g. performing 
-that depend on knowing that the operators have restricted type inputs.  The second
+optimizations that depend on knowing that the operators have restricted type 
-pass cleans up the messy code generated by the Legalize pass, allowing Legalize to
+inputs).  The second run of the pass cleans up the messy code generated by the 
-be very simple (not having to take into account many special cases.
+Legalize pass, allowing Legalize to be very simple since it can ignore many 
+special cases. 
 </p>
 
 <p>
@@ -838,8 +851,8 @@ International Conference on Compiler Construction (CC) 2004
 <p>The Select phase is the bulk of the target-specific code for instruction
 selection.  This phase takes a legal SelectionDAG as input, and does simple
 pattern matching on the DAG to generate code.  In time, the Select phase will
-be automatically generated from the targets InstrInfo.td file, which is why we
+be automatically generated from the target's InstrInfo.td file, which is why we
-want to make the Select phase a simple and mechanical as possible.</p>
+want to make the Select phase as simple and mechanical as possible.</p>
 
 </div>
 
@@ -853,13 +866,39 @@ want to make the Select phase a simple and mechanical as possible.</p>
 <ol>
 <li>Optional whole-function selection.</li>
 <li>Select is a graph translation phase.</li>
-<li>Place the machine instrs resulting from Select according to register pressure or a schedule.</li>
+<li>Place the machine instructions resulting from Select according to register 
+pressure or a schedule.</li>
 <li>DAG Scheduling.</li>
-<li>Auto-generate the Select phase from the target .td files.</li>
+<li>Auto-generate the Select phase from the target description (*.td) files.
+</li>
 </ol>
 
 </div>
-
+ 
+<!-- ======================================================================= -->
+<div class="doc_subsection">
+  <a name="ssamco">SSA-based Machine Code Optimizations</a>
+</div>
+<div class="doc_text"><p>To Be Written</p></div>
+<!-- ======================================================================= -->
+<div class="doc_subsection">
+  <a name="regalloc">Register Allocation</a>
+</div>
+<div class="doc_text"><p>To Be Written</p></div>
+<!-- ======================================================================= -->
+<div class="doc_subsection">
+  <a name="proepicode">Prolog/Epilog Code Insertion</a>
+</div>
+<div class="doc_text"><p>To Be Written</p></div>
+<!-- ======================================================================= -->
+<div class="doc_subsection">
+  <a name="latemco">Late Machine Code Optimizations</a>
+</div>
+<div class="doc_text"><p>To Be Written</p></div>
+<!-- ======================================================================= -->
+<div class="doc_subsection">
+  <a name="codemission">Code Emission</a>
+</div>
 
 <!-- *********************************************************************** -->
 <div class="doc_section">
@@ -869,7 +908,7 @@ want to make the Select phase a simple and mechanical as possible.</p>
 
 <div class="doc_text">
 
-<p>This section of the document explains any features or design decisions that
+<p>This section of the document explains features or design decisions that
 are specific to the code generator for a particular target.</p>
 
 </div>
@@ -917,8 +956,8 @@ Meaning:   DestReg, | BaseReg,  Scale, IndexReg, Displacement
 OperandTy: VirtReg, | VirtReg, UnsImm, VirtReg,   SignExtImm
 </pre>
 
-<p>Stores and all other instructions treat the four memory operands in the same
+<p>Stores, and all other instructions, treat the four memory operands in the 
-way, in the same order.</p>
+same way, in the same order.</p>
 
 </div>
 
@@ -930,9 +969,8 @@ way, in the same order.</p>
 <div class="doc_text">
 
 <p>
-An instruction name consists of the base name, a default operand size
+An instruction name consists of the base name, a default operand size, and a
-followed by a character per operand with an optional special size. For
+a character per operand with an optional special size. For example:</p>
-example:</p>
 
 <p>
 <tt>ADD8rr</tt> -&gt; add, 8-bit register, 8-bit register<br>