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MIR Serialization: Serialize the virtual register definitions.
The virtual registers are serialized using a YAML sequence of YAML inline mappings. Each mapping has the id of the virtual register and the register class. Reviewers: Duncan P. N. Exon Smith Differential Revision: http://reviews.llvm.org/D10981 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241868 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -42,7 +42,8 @@ public:
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void print(const MachineFunction &MF);
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void convert(yaml::MachineFunction &MF, const MachineRegisterInfo &RegInfo);
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void convert(yaml::MachineFunction &MF, const MachineRegisterInfo &RegInfo,
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const TargetRegisterInfo *TRI);
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void convert(yaml::MachineFrameInfo &YamlMFI, const MachineFrameInfo &MFI);
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void convert(ModuleSlotTracker &MST, yaml::MachineBasicBlock &YamlMBB,
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const MachineBasicBlock &MBB);
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@ -95,7 +96,7 @@ void MIRPrinter::print(const MachineFunction &MF) {
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YamlMF.Alignment = MF.getAlignment();
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YamlMF.ExposesReturnsTwice = MF.exposesReturnsTwice();
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YamlMF.HasInlineAsm = MF.hasInlineAsm();
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convert(YamlMF, MF.getRegInfo());
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convert(YamlMF, MF.getRegInfo(), MF.getSubtarget().getRegisterInfo());
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convert(YamlMF.FrameInfo, *MF.getFrameInfo());
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int I = 0;
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@ -117,10 +118,21 @@ void MIRPrinter::print(const MachineFunction &MF) {
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}
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void MIRPrinter::convert(yaml::MachineFunction &MF,
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const MachineRegisterInfo &RegInfo) {
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const MachineRegisterInfo &RegInfo,
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const TargetRegisterInfo *TRI) {
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MF.IsSSA = RegInfo.isSSA();
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MF.TracksRegLiveness = RegInfo.tracksLiveness();
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MF.TracksSubRegLiveness = RegInfo.subRegLivenessEnabled();
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// Print the virtual register definitions.
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for (unsigned I = 0, E = RegInfo.getNumVirtRegs(); I < E; ++I) {
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unsigned Reg = TargetRegisterInfo::index2VirtReg(I);
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yaml::VirtualRegisterDefinition VReg;
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VReg.ID = I;
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VReg.Class =
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StringRef(TRI->getRegClassName(RegInfo.getRegClass(Reg))).lower();
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MF.VirtualRegisters.push_back(VReg);
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}
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}
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void MIRPrinter::convert(yaml::MachineFrameInfo &YamlMFI,
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