[projects/test-suite] White space and long line fixes.

No functionality changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192863 91177308-0d34-0410-b5e6-96231b3b80d8

include/llvm/Target/TargetLowering.h

@@ -576,7 +576,7 @@ public:
       VectorType *VTy = cast<VectorType>(Ty);
       Type *Elm = VTy->getElementType();
       // Lower vectors of pointers to native pointer types.
-      if (Elm->isPointerTy()) 
+      if (Elm->isPointerTy())
         Elm = EVT(PointerTy).getTypeForEVT(Ty->getContext());
       return EVT::getVectorVT(Ty->getContext(), EVT::getEVT(Elm, false),
                        VTy->getNumElements());
@@ -1185,11 +1185,12 @@ public:
 
   /// Return true if the target supplies and combines to a paired load
   /// two loaded values of type LoadedType next to each other in memory.
-  /// RequiredAlignment gives the minimal alignment constraints that must be met to
+  /// RequiredAlignment gives the minimal alignment constraints that must be met
-  /// be able to select this paired load.
+  /// to be able to select this paired load.
   ///
-  /// This information is *not* used to generate actual paired loads, but it is used
+  /// This information is *not* used to generate actual paired loads, but it is
-  /// to generate a sequence of loads that is easier to combine into a paired load.
+  /// used to generate a sequence of loads that is easier to combine into a
+  /// paired load.
   /// For instance, something like this:
   /// a = load i64* addr
   /// b = trunc i64 a to i32
@@ -1200,8 +1201,9 @@ public:
   /// d = load i32* addr2
   /// Where addr1 = addr2 +/- sizeof(i32).
   ///
-  /// In other words, unless the target performs a post-isel load combining, this 
+  /// In other words, unless the target performs a post-isel load combining,
-  /// information should not be provided because it will generate more loads.
+  /// this information should not be provided because it will generate more
+  /// loads.
   virtual bool hasPairedLoad(Type * /*LoadedType*/,
                              unsigned & /*RequiredAligment*/) const {
     return false;
@@ -1502,7 +1504,7 @@ public:
     if (NumElts == 1)
       return LegalizeKind(TypeScalarizeVector, EltVT);
 
-    // Try to widen vector elements until the element type is a power of two and 
+    // Try to widen vector elements until the element type is a power of two and
     // promote it to a legal type later on, for example:
     // <3 x i8> -> <4 x i8> -> <4 x i32>
     if (EltVT.isInteger()) {
@@ -1536,7 +1538,8 @@ public:
 
         // Stop trying when getting a non-simple element type.
         // Note that vector elements may be greater than legal vector element
-        // types. Example: X86 XMM registers hold 64bit element on 32bit systems.
+        // types. Example: X86 XMM registers hold 64bit element on 32bit
+        // systems.
         if (!EltVT.isSimple()) break;
 
         // Build a new vector type and check if it is legal.
@@ -1697,7 +1700,8 @@ public:
   /// by reference if this node can be combined with a load / store to form a
   /// post-indexed load / store.
   virtual bool getPostIndexedAddressParts(SDNode * /*N*/, SDNode * /*Op*/,
-                                          SDValue &/*Base*/, SDValue &/*Offset*/,
+                                          SDValue &/*Base*/,
+                                          SDValue &/*Offset*/,
                                           ISD::MemIndexedMode &/*AM*/,
                                           SelectionDAG &/*DAG*/) const {
     return false;

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

@@ -349,7 +349,8 @@ namespace {
       assert(LHSTy.isInteger() && "Shift amount is not an integer type!");
       if (LHSTy.isVector())
         return LHSTy;
-      return LegalTypes ? TLI.getScalarShiftAmountTy(LHSTy) : TLI.getPointerTy();
+      return LegalTypes ? TLI.getScalarShiftAmountTy(LHSTy)
+                        : TLI.getPointerTy();
     }
 
     /// isTypeLegal - This method returns true if we are running before type
@@ -1037,7 +1038,8 @@ void DAGCombiner::Run(CombineLevel AtLevel) {
   // try and combine it.
   while (!WorkListContents.empty()) {
     SDNode *N;
-    // The WorkListOrder holds the SDNodes in order, but it may contain duplicates.
+    // The WorkListOrder holds the SDNodes in order, but it may contain
+    // duplicates.
     // In order to avoid a linear scan, we use a set (O(log N)) to hold what the
     // worklist *should* contain, and check the node we want to visit is should
     // actually be visited.
@@ -1791,8 +1793,8 @@ SDValue DAGCombiner::visitSUBE(SDNode *N) {
   return SDValue();
 }
 
-/// isConstantSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are
+/// isConstantSplatVector - Returns true if N is a BUILD_VECTOR node whose
-/// all the same constant or undefined.
+/// elements are all the same constant or undefined.
 static bool isConstantSplatVector(SDNode *N, APInt& SplatValue) {
   BuildVectorSDNode *C = dyn_cast<BuildVectorSDNode>(N);
   if (!C)
@@ -1828,9 +1830,11 @@ SDValue DAGCombiner::visitMUL(SDNode *N) {
     N1IsConst = isConstantSplatVector(N1.getNode(), ConstValue1);
   } else {
     N0IsConst = dyn_cast<ConstantSDNode>(N0) != 0;
-    ConstValue0 = N0IsConst? (dyn_cast<ConstantSDNode>(N0))->getAPIntValue() : APInt();
+    ConstValue0 = N0IsConst ? (dyn_cast<ConstantSDNode>(N0))->getAPIntValue()
+                            : APInt();
     N1IsConst = dyn_cast<ConstantSDNode>(N1) != 0;
-    ConstValue1 = N1IsConst? (dyn_cast<ConstantSDNode>(N1))->getAPIntValue() : APInt();
+    ConstValue1 = N1IsConst ? (dyn_cast<ConstantSDNode>(N1))->getAPIntValue()
+                            : APInt();
   }
 
   // fold (mul c1, c2) -> c1*c2
@@ -3442,8 +3446,8 @@ SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, SDLoc DL) {
                 DAG.getNode(HasROTLWithLArg ? ISD::ROTL : ISD::ROTR, DL, LArgVT,
                             LArgExtOp0, HasROTL ? LHSShiftAmt : RHSShiftAmt);
             return DAG.getNode(LHSShiftArg.getOpcode(), DL, VT, V).getNode();
-          }     
+          }
-        }     
+        }
       }
     }
   } else if (LExtOp0.getOpcode() == ISD::SUB &&
@@ -4691,9 +4695,9 @@ SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
          TLI.isOperationLegal(ISD::SETCC, getSetCCResultType(VT)))) {
       return DAG.getSelect(SDLoc(N), VT,
                            DAG.getSetCC(SDLoc(N),
-                                        getSetCCResultType(VT),
+                           getSetCCResultType(VT),
-                                        N0.getOperand(0), N0.getOperand(1),
+                           N0.getOperand(0), N0.getOperand(1),
-                                        cast<CondCodeSDNode>(N0.getOperand(2))->get()),
+                           cast<CondCodeSDNode>(N0.getOperand(2))->get()),
                            NegOne, DAG.getConstant(0, VT));
     }
   }
@@ -9891,7 +9895,8 @@ SDValue DAGCombiner::visitEXTRACT_SUBVECTOR(SDNode* N) {
     //    (extract_subvec (concat V1, V2, ...), i)
     // Into:
     //    Vi if possible
-    // Only operand 0 is checked as 'concat' assumes all inputs of the same type.
+    // Only operand 0 is checked as 'concat' assumes all inputs of the same
+    // type.
     if (V->getOperand(0).getValueType() != NVT)
       return SDValue();
     unsigned Idx = dyn_cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
@@ -10640,9 +10645,10 @@ SDValue DAGCombiner::SimplifySelectCC(SDLoc DL, SDValue N0, SDValue N1,
         return Temp;
 
       // shl setcc result by log2 n2c
-      return DAG.getNode(ISD::SHL, DL, N2.getValueType(), Temp,
+      return DAG.getNode(
-                         DAG.getConstant(N2C->getAPIntValue().logBase2(),
+          ISD::SHL, DL, N2.getValueType(), Temp,
-                                         getShiftAmountTy(Temp.getValueType())));
+          DAG.getConstant(N2C->getAPIntValue().logBase2(),
+                          getShiftAmountTy(Temp.getValueType())));
     }
   }