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[ARM64] PR19792: Fix cycle in DAG after performPostLD1Combine

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Povray and dealII currently assert with "Overran sorted position" in
AssignTopologicalOrder.  The problem is that performPostLD1Combine can
introduce cycles.

Consider:

(insert_vector_elt (INSERT_SUBREG undef,
                                  (load (add %vreg0, Constant<8>), undef),  <= A
                                  TargetConstant<2>),
                   (load %vreg0, undef),                                    <= B
                   Constant<1>)

This is turned into a LD1LANEpost node.  However the address in A is not a
valid user of the post-incremented address of B in LD1LANEpost.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209242 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Adam Nemet 2014-05-20 21:47:07 +00:00
parent e94103adcd
commit adf1668bec
2 changed files with 46 additions and 1 deletions
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7
lib/Target/ARM64/ARM64ISelLowering.cpp
View File

@ -7298,6 +7298,7 @@ static SDValue performPostLD1Combine(SDNode *N,
}
SDValue Addr = LD->getOperand(1);
SDValue Vector = N->getOperand(0);
// Search for a use of the address operand that is an increment.
for (SDNode::use_iterator UI = Addr.getNode()->use_begin(), UE =
Addr.getNode()->use_end(); UI != UE; ++UI) {
@ -7310,6 +7311,10 @@ static SDValue performPostLD1Combine(SDNode *N,
// would create a cycle.
if (User->isPredecessorOf(LD) || LD->isPredecessorOf(User))
continue;
// Also check that add is not used in the vector operand. This would also
// create a cycle.
if (User->isPredecessorOf(Vector.getNode()))
continue;
// If the increment is a constant, it must match the memory ref size.
SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
@ -7324,7 +7329,7 @@ static SDValue performPostLD1Combine(SDNode *N,
SmallVector<SDValue, 8> Ops;
Ops.push_back(LD->getOperand(0)); // Chain
if (IsLaneOp) {
Ops.push_back(N->getOperand(0)); // The vector to be inserted
Ops.push_back(Vector); // The vector to be inserted
Ops.push_back(N->getOperand(2)); // The lane to be inserted in the vector
}
Ops.push_back(Addr);

40
test/CodeGen/ARM64/indexed-vector-ldst-2.ll Normal file
View File

@ -0,0 +1,40 @@
; RUN: llc %s
; This used to assert with "Overran sorted position" in AssignTopologicalOrder
; due to a cycle created in performPostLD1Combine.
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
target triple = "arm64-apple-ios7.0.0"
; Function Attrs: nounwind ssp
define void @f(double* %P1) #0 {
entry:
%arrayidx4 = getelementptr inbounds double* %P1, i64 1
%0 = load double* %arrayidx4, align 8, !tbaa !1
%1 = load double* %P1, align 8, !tbaa !1
%2 = insertelement <2 x double> undef, double %0, i32 0
%3 = insertelement <2 x double> %2, double %1, i32 1
%4 = fsub <2 x double> zeroinitializer, %3
%5 = fmul <2 x double> undef, %4
%6 = extractelement <2 x double> %5, i32 0
%cmp168 = fcmp olt double %6, undef
br i1 %cmp168, label %if.then172, label %return
if.then172: ; preds = %cond.end90
%7 = tail call i64 @llvm.objectsize.i64.p0i8(i8* undef, i1 false)
br label %return
return: ; preds = %if.then172, %cond.end90, %entry
ret void
}
; Function Attrs: nounwind readnone
declare i64 @llvm.objectsize.i64.p0i8(i8*, i1) #1
attributes #0 = { nounwind ssp "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
attributes #1 = { nounwind readnone }
!1 = metadata !{metadata !2, metadata !2, i64 0}
!2 = metadata !{metadata !"double", metadata !3, i64 0}
!3 = metadata !{metadata !"omnipotent char", metadata !4, i64 0}
!4 = metadata !{metadata !"Simple C/C++ TBAA"}