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ARM RSCS* don't need explicit TableGen decoder checks.

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They've been pseudos for a while now, so the decoder will never see
them in the first place.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134101 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach 2011-06-29 22:01:15 +00:00
parent 33b259f46c
commit ae218dee5e
1 changed files with 0 additions and 4 deletions
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4
utils/TableGen/ARMDecoderEmitter.cpp
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@ -1592,10 +1592,6 @@ ARMDEBackend::populateInstruction(const CodeGenInstruction &CGI,
// The following special cases are for conflict resolutions.
//
// RSCSri and RSCSrs set the 's' bit, but are not predicated. We are
// better off using the generic RSCri and RSCrs instructions.
if (Name == "RSCSri" || Name == "RSCSrs") return false;
// A8-598: VEXT
// Vector Extract extracts elements from the bottom end of the second
// operand vector and the top end of the first, concatenates them and