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ARM: enforce SRS decoding constraints

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183611 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Amaury de la Vieuville
2013-06-08 13:43:59 +00:00
parent 46e136c952
commit ae50ddb2ae
2 changed files with 14 additions and 4 deletions
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8
lib/Target/ARM/Disassembler/ARMDisassembler.cpp
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@@ -1768,6 +1768,7 @@ static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst,
unsigned reglist = fieldFromInstruction(Insn, 0, 16);
if (pred == 0xF) {
// Ambiguous with RFE and SRS
switch (Inst.getOpcode()) {
case ARM::LDMDA:
Inst.setOpcode(ARM::RFEDA);
@@ -1818,11 +1819,16 @@ static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst,
Inst.setOpcode(ARM::SRSIB_UPD);
break;
default:
if (!Check(S, MCDisassembler::Fail)) return MCDisassembler::Fail;
return MCDisassembler::Fail;
}
// For stores (which become SRS's, the only operand is the mode.
if (fieldFromInstruction(Insn, 20, 1) == 0) {
// Check SRS encoding constraints
if (!(fieldFromInstruction(Insn, 22, 1) == 1 &&
fieldFromInstruction(Insn, 20, 1) == 0))
return MCDisassembler::Fail;
Inst.addOperand(
MCOperand::CreateImm(fieldFromInstruction(Insn, 0, 4)));
return S;