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[mips][mips64r6] ll, sc, lld, and scd are re-encoded on MIPS32r6/MIPS64r6.
Summary: The linked-load, store-conditional operations have been re-encoded such that have a 9-bit offset instead of the 16-bit offset they have prior to MIPS32r6/MIPS64r6. While implementing this, I noticed that the atomic load/store pseudos always emit a sign extension using sll and sra. I have improved this to use seb/seh when they are available (MIPS32r2/MIPS64r2 and above). Depends on D4118 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D4119 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211018 91177308-0d34-0410-b5e6-96231b3b80d8
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@@ -272,6 +272,11 @@ static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeSimm16(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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@@ -1068,6 +1073,27 @@ static DecodeStatus DecodeFMem(MCInst &Inst,
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst,
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unsigned Insn,
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uint64_t Address,
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const void *Decoder) {
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int64_t Offset = SignExtend64<9>((Insn >> 7) & 0x1ff);
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unsigned Rt = fieldFromInstruction(Insn, 16, 5);
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unsigned Base = fieldFromInstruction(Insn, 21, 5);
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Rt = getReg(Decoder, Mips::GPR32RegClassID, Rt);
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Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
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if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){
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Inst.addOperand(MCOperand::CreateReg(Rt));
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}
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Inst.addOperand(MCOperand::CreateReg(Rt));
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Inst.addOperand(MCOperand::CreateReg(Base));
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Inst.addOperand(MCOperand::CreateImm(Offset));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
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unsigned RegNo,
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