6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-06-12 13:38:21 +00:00
Code Issues Projects Releases Wiki Activity

Make the -verify-regalloc command line option available to base classes as

Browse Source 
RegAllocBase::VerifyEnabled.

Run the machine code verifier in a few interesting places during RegAllocGreedy.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@122107 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen
2010-12-17 23:16:35 +00:00
parent f428eb6c1b
commit af24964251
3 changed files with 15 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
lib/CodeGen/RegAllocBasic.cpp
View File

@ -53,11 +53,12 @@ static RegisterRegAlloc basicRegAlloc("basic", "basic register allocator",
// Temporary verification option until we can put verification inside
// MachineVerifier.
static cl::opt<bool>
VerifyRegAlloc("verify-regalloc",
cl::desc("Verify live intervals before renaming"));
static cl::opt<bool, true>
VerifyRegAlloc("verify-regalloc", cl::location(RegAllocBase::VerifyEnabled),
cl::desc("Verify during register allocation"));
const char *RegAllocBase::TimerGroupName = "Register Allocation";
bool RegAllocBase::VerifyEnabled = false;
namespace {
/// RABasic provides a minimal implementation of the basic register allocation
@ -475,7 +476,7 @@ bool RABasic::runOnMachineFunction(MachineFunction &mf) {
// make the rewriter a separate pass and override verifyAnalysis instead. When
// that happens, verification naturally falls under VerifyMachineCode.
#ifndef NDEBUG
if (VerifyRegAlloc) {
if (VerifyEnabled) {
// Verify accuracy of LiveIntervals. The standard machine code verifier
// ensures that each LiveIntervals covers all uses of the virtual reg.