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Add encoding for ARM "trap" instruction.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119938 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Wendling 2010-11-21 11:05:29 +00:00
parent 9717fa9f29
commit af2b573614
4 changed files with 9 additions and 5 deletions
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5
lib/Target/ARM/ARMInstrInfo.td
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@ -1130,10 +1130,7 @@ let isBarrier = 1, isTerminator = 1 in
def TRAP : AXI<(outs), (ins), MiscFrm, NoItinerary,
"trap", [(trap)]>,
Requires<[IsARM]> {
let Inst{27-25} = 0b011;
let Inst{24-20} = 0b11111;
let Inst{7-5} = 0b111;
let Inst{4} = 0b1;
let Inst = 0xe7ffdefe;
}
// Address computation and loads and stores in PIC mode.

4
test/MC/ARM/arm_instructions.s
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@ -8,6 +8,10 @@
@ CHECK: encoding: [0x00,0xf0,0x20,0x03]
nopeq
@ CHECK: trap
@ CHECK: encoding: [0xfe,0xde,0xff,0xe7]
trap
@ CHECK: bx lr
@ CHECK: encoding: [0x1e,0xff,0x2f,0xe1]
bx lr

2
test/MC/ARM/simple-encoding.ll
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@ -12,7 +12,7 @@ declare i32 @llvm.ctlz.i32(i32)
define i32 @foo(i32 %a, i32 %b) {
; CHECK: foo
; CHECK: trap @ encoding: [0xf0,0x00,0xf0,0x07]
; CHECK: trap @ encoding: [0xfe,0xde,0xff,0xe7]
; CHECK: bx lr @ encoding: [0x1e,0xff,0x2f,0xe1]
tail call void @llvm.trap()

3
test/MC/ARM/thumb.s
View File

@ -6,3 +6,6 @@
@ CHECK: pop {r1, r2, r4} @ encoding: [0x16,0xbc]
pop {r1, r2, r4}
@ CHECK: trap @ encoding: [0xfe,0xde]
trap