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Go through all kinds of trouble to mark 'blr' as having a predicate operand

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that takes a register and condition code.  Print these pieces of BLR the
right way, even though it is currently set to 'always'.

Next up: get the JIT encoding right, then enhance branch folding to produce
predicated blr for simple examples.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31449 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
2006-11-04 05:27:39 +00:00
parent efe9f4a3b6
commit af53a87052
3 changed files with 63 additions and 13 deletions
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13
lib/Target/PowerPC/PPCInstrInfo.td
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@@ -255,9 +255,11 @@ def memrix : Operand<iPTR> { // memri where the imm is shifted 2 bits.
let MIOperandInfo = (ops i32imm, ptr_rc);
}
// PowerPC Predicate operand. 20 = always, CR0 is a dummy reg that doesn't
// matter.
def pred : PredicateOperand<(ops imm, CRRC), (ops 20, CR0)>;
// PowerPC Predicate operand. 640 = ((20<<5)|0) = always, CR0 is a dummy reg
// that doesn't matter.
def pred : PredicateOperand<(ops imm, CRRC), (ops (i32 640), CR0)> {
let PrintMethod = "printPredicateOperand";
}
// Define PowerPC specific addressing mode.
def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>;
@@ -315,10 +317,13 @@ let usesCustomDAGSchedInserter = 1, // Expanded by the scheduler.
let isTerminator = 1, isBarrier = 1, noResults = 1, PPC970_Unit = 7 in {
let isReturn = 1 in
def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (ops), "blr", BrB, [(retflag)]>;
def BLR : XLForm_2_ext<19, 16, 20, 0, 0,
(ops pred:$p),
"b${p:cc}lr ${p:reg}", BrB, [(retflag)]>;
def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (ops), "bctr", BrB, []>;
}
let Defs = [LR] in
def MovePCtoLR : Pseudo<(ops piclabel:$label), "bl $label", []>,
PPC970_Unit_BRU;