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Don't create rotate instructions in unsupported types, because we don't have

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promote/expand code yet.  This fixes the 177.mesa failure on PPC.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25250 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2006-01-12 18:57:33 +00:00
parent 4bb91024ac
commit af551bcf6b
1 changed files with 2 additions and 2 deletions
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4
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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@ -1184,7 +1184,7 @@ SDOperand DAGCombiner::visitOR(SDNode *N) {
// check for rotl, rotr // check for rotl, rotr
if (N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SRL && if (N0.getOpcode() == ISD::SHL && N1.getOpcode() == ISD::SRL &&
N0.getOperand(0) == N1.getOperand(0) && N0.getOperand(0) == N1.getOperand(0) &&
TLI.isOperationLegal(ISD::ROTL, VT)) { TLI.isOperationLegal(ISD::ROTL, VT) && TLI.isTypeLegal(VT)) {
// fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1) // fold (or (shl x, C1), (srl x, C2)) -> (rotl x, C1)
if (N0.getOperand(1).getOpcode() == ISD::Constant && if (N0.getOperand(1).getOpcode() == ISD::Constant &&
N1.getOperand(1).getOpcode() == ISD::Constant) { N1.getOperand(1).getOpcode() == ISD::Constant) {
@ -1206,7 +1206,7 @@ SDOperand DAGCombiner::visitOR(SDNode *N) {
if (ConstantSDNode *SUBC = if (ConstantSDNode *SUBC =
dyn_cast<ConstantSDNode>(N0.getOperand(1).getOperand(0))) dyn_cast<ConstantSDNode>(N0.getOperand(1).getOperand(0)))
if (SUBC->getValue() == OpSizeInBits) { if (SUBC->getValue() == OpSizeInBits) {
if (TLI.isOperationLegal(ISD::ROTR, VT)) if (TLI.isOperationLegal(ISD::ROTR, VT) && TLI.isTypeLegal(VT))
return DAG.getNode(ISD::ROTR, VT, N0.getOperand(0), return DAG.getNode(ISD::ROTR, VT, N0.getOperand(0),
N1.getOperand(1)); N1.getOperand(1));
else else