6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-28 19:31:58 +00:00
Code Issues Projects Releases Wiki Activity

R600: Anti dep better handled in tex clause

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183592 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Vincent Lejeune 2013-06-07 23:30:26 +00:00
parent ec2aaad01b
commit b01bdf87ff
2 changed files with 28 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
lib/Target/R600/R600ControlFlowFinalizer.cpp
View File

@ -110,7 +110,7 @@ private:
}
bool isCompatibleWithClause(const MachineInstr *MI,
std::set<unsigned> &DstRegs, std::set<unsigned> &SrcRegs) const {
std::set<unsigned> &DstRegs) const {
unsigned DstMI, SrcMI;
for (MachineInstr::const_mop_iterator I = MI->operands_begin(),
E = MI->operands_end(); I != E; ++I) {
@ -136,9 +136,7 @@ private:
&AMDGPU::R600_Reg128RegClass);
}
}
if ((DstRegs.find(SrcMI) == DstRegs.end()) &&
(SrcRegs.find(DstMI) == SrcRegs.end())) {
SrcRegs.insert(SrcMI);
if ((DstRegs.find(SrcMI) == DstRegs.end())) {
DstRegs.insert(DstMI);
return true;
} else
@ -152,7 +150,7 @@ private:
std::vector<MachineInstr *> ClauseContent;
unsigned AluInstCount = 0;
bool IsTex = TII->usesTextureCache(ClauseHead);
std::set<unsigned> DstRegs, SrcRegs;
std::set<unsigned> DstRegs;
for (MachineBasicBlock::iterator E = MBB.end(); I != E; ++I) {
if (IsTrivialInst(I))
continue;
@ -161,7 +159,7 @@ private:
if ((IsTex && !TII->usesTextureCache(I)) ||
(!IsTex && !TII->usesVertexCache(I)))
break;
if (!isCompatibleWithClause(I, DstRegs, SrcRegs))
if (!isCompatibleWithClause(I, DstRegs))
break;
AluInstCount ++;
ClauseContent.push_back(I);

24
test/CodeGen/R600/tex-clause-antidep.ll Normal file
View File

@ -0,0 +1,24 @@
;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
;CHECK: TEX
;CHECK-NEXT: ALU
define void @test() {
%1 = call float @llvm.R600.load.input(i32 0)
%2 = call float @llvm.R600.load.input(i32 1)
%3 = call float @llvm.R600.load.input(i32 2)
%4 = call float @llvm.R600.load.input(i32 3)
%5 = insertelement <4 x float> undef, float %1, i32 0
%6 = insertelement <4 x float> %5, float %2, i32 1
%7 = insertelement <4 x float> %6, float %3, i32 2
%8 = insertelement <4 x float> %7, float %4, i32 3
%9 = call <4 x float> @llvm.R600.tex(<4 x float> %8, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
%10 = call <4 x float> @llvm.R600.tex(<4 x float> %8, i32 1, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0)
%11 = fadd <4 x float> %9, %10
call void @llvm.R600.store.swizzle(<4 x float> %11, i32 0, i32 0)
ret void
}
declare float @llvm.R600.load.input(i32) readnone
declare <4 x float> @llvm.R600.tex(<4 x float>, i32, i32, i32, i32, i32, i32, i32, i32, i32) readnone
declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)