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Tidy up a few 80 column violations.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139636 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
2011-09-13 20:30:37 +00:00
parent 8f310d9786
commit b04546ff5b
5 changed files with 17 additions and 17 deletions
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6
lib/Target/ARM/ARMFastISel.cpp
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@@ -615,8 +615,8 @@ unsigned ARMFastISel::ARMMaterializeGV(const GlobalValue *GV, EVT VT) {
if (Subtarget->GVIsIndirectSymbol(GV, RelocM)) { if (Subtarget->GVIsIndirectSymbol(GV, RelocM)) {
unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT)); unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT));
if (isThumb) if (isThumb)
MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::t2LDRi12), MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
NewDestReg) TII.get(ARM::t2LDRi12), NewDestReg)
.addReg(DestReg) .addReg(DestReg)
.addImm(0); .addImm(0);
else else
@@ -1719,7 +1719,7 @@ bool ARMFastISel::SelectRet(const Instruction *I) {
// Analyze operands of the call, assigning locations to each operand. // Analyze operands of the call, assigning locations to each operand.
SmallVector<CCValAssign, 16> ValLocs; SmallVector<CCValAssign, 16> ValLocs;
CCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, TM, ValLocs, I->getContext()); CCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, TM, ValLocs,I->getContext());
CCInfo.AnalyzeReturn(Outs, CCAssignFnForCall(CC, true /* is Ret */)); CCInfo.AnalyzeReturn(Outs, CCAssignFnForCall(CC, true /* is Ret */));
const Value *RV = Ret->getOperand(0); const Value *RV = Ret->getOperand(0);

8
lib/Target/ARM/ARMISelDAGToDAG.cpp
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@@ -1390,15 +1390,15 @@ SDNode *ARMDAGToDAGISel::SelectARMIndexedLoad(SDNode *N) {
SDValue Base = LD->getBasePtr(); SDValue Base = LD->getBasePtr();
SDValue Ops[]= { Base, AMOpc, getAL(CurDAG), SDValue Ops[]= { Base, AMOpc, getAL(CurDAG),
CurDAG->getRegister(0, MVT::i32), Chain }; CurDAG->getRegister(0, MVT::i32), Chain };
return CurDAG->getMachineNode(Opcode, N->getDebugLoc(), MVT::i32, MVT::i32, return CurDAG->getMachineNode(Opcode, N->getDebugLoc(), MVT::i32,
MVT::Other, Ops, 5); MVT::i32, MVT::Other, Ops, 5);
} else { } else {
SDValue Chain = LD->getChain(); SDValue Chain = LD->getChain();
SDValue Base = LD->getBasePtr(); SDValue Base = LD->getBasePtr();
SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG), SDValue Ops[]= { Base, Offset, AMOpc, getAL(CurDAG),
CurDAG->getRegister(0, MVT::i32), Chain }; CurDAG->getRegister(0, MVT::i32), Chain };
return CurDAG->getMachineNode(Opcode, N->getDebugLoc(), MVT::i32, MVT::i32, return CurDAG->getMachineNode(Opcode, N->getDebugLoc(), MVT::i32,
MVT::Other, Ops, 6); MVT::i32, MVT::Other, Ops, 6);
} }
} }

5
lib/Target/ARM/ARMISelLowering.cpp
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@@ -2775,7 +2775,7 @@ SDValue ARMTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
SDValue ARMcc; SDValue ARMcc;
SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32); SDValue CCR = DAG.getRegister(ARM::CPSR, MVT::i32);
SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl); SDValue Cmp = getARMCmp(LHS, RHS, CC, ARMcc, DAG, dl);
return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR, Cmp); return DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, TrueVal, ARMcc, CCR,Cmp);
} }
ARMCC::CondCodes CondCode, CondCode2; ARMCC::CondCodes CondCode, CondCode2;
@@ -7252,7 +7252,8 @@ ARMTargetLowering::PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const {
SDValue FalseVal = N->getOperand(0); SDValue FalseVal = N->getOperand(0);
SDValue TrueVal = N->getOperand(1); SDValue TrueVal = N->getOperand(1);
SDValue ARMcc = N->getOperand(2); SDValue ARMcc = N->getOperand(2);
ARMCC::CondCodes CC = (ARMCC::CondCodes)cast<ConstantSDNode>(ARMcc)->getZExtValue(); ARMCC::CondCodes CC =
(ARMCC::CondCodes)cast<ConstantSDNode>(ARMcc)->getZExtValue();
// Simplify // Simplify
// mov r1, r0 // mov r1, r0

13
lib/Target/ARM/ARMSelectionDAGInfo.cpp
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@@ -138,13 +138,12 @@ ARMSelectionDAGInfo::EmitTargetCodeForMemcpy(SelectionDAG &DAG, DebugLoc dl,
// Adjust parameters for memset, EABI uses format (ptr, size, value), // Adjust parameters for memset, EABI uses format (ptr, size, value),
// GNU library uses (ptr, value, size) // GNU library uses (ptr, value, size)
// See RTABI section 4.3.4 // See RTABI section 4.3.4
SDValue SDValue ARMSelectionDAGInfo::
ARMSelectionDAGInfo::EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl, EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl,
SDValue Chain, SDValue Dst, SDValue Chain, SDValue Dst,
SDValue Src, SDValue Size, SDValue Src, SDValue Size,
unsigned Align, bool isVolatile, unsigned Align, bool isVolatile,
MachinePointerInfo DstPtrInfo) const MachinePointerInfo DstPtrInfo) const {
{
// Use default for non AAPCS subtargets // Use default for non AAPCS subtargets
if (!Subtarget->isAAPCS_ABI()) if (!Subtarget->isAAPCS_ABI())
return SDValue(); return SDValue();

2
lib/Target/ARM/Thumb1FrameLowering.cpp
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@@ -21,7 +21,7 @@
using namespace llvm; using namespace llvm;
bool Thumb1FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const { bool Thumb1FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const{
const MachineFrameInfo *FFI = MF.getFrameInfo(); const MachineFrameInfo *FFI = MF.getFrameInfo();
unsigned CFSize = FFI->getMaxCallFrameSize(); unsigned CFSize = FFI->getMaxCallFrameSize();
// It's not always a good idea to include the call frame as part of the // It's not always a good idea to include the call frame as part of the