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ComputeKnownBits: be a bit smarter about ADDs

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If our two inputs have known top-zero bit counts M and N, we trivially
know that the output cannot have any bits set in the top (min(M, N)-1)
bits, since nothing could carry past that point.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241927 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Fiona Glaser
2015-07-10 18:29:02 +00:00
parent 02e89ace70
commit b0a2d8c5a5
3 changed files with 22 additions and 12 deletions
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19
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
View File

@@ -2356,15 +2356,24 @@ void SelectionDAG::computeKnownBits(SDValue Op, APInt &KnownZero,
// Output known-0 bits are known if clear or set in both the low clear bits // Output known-0 bits are known if clear or set in both the low clear bits
// common to both LHS & RHS. For example, 8+(X<<3) is known to have the // common to both LHS & RHS. For example, 8+(X<<3) is known to have the
// low 3 bits clear. // low 3 bits clear.
// Output known-0 bits are also known if the top bits of each input are
// known to be clear. For example, if one input has the top 10 bits clear
// and the other has the top 8 bits clear, we know the top 7 bits of the
// output must be clear.
computeKnownBits(Op.getOperand(0), KnownZero2, KnownOne2, Depth+1); computeKnownBits(Op.getOperand(0), KnownZero2, KnownOne2, Depth+1);
unsigned KnownZeroOut = KnownZero2.countTrailingOnes(); unsigned KnownZeroHigh = KnownZero2.countLeadingOnes();
unsigned KnownZeroLow = KnownZero2.countTrailingOnes();
computeKnownBits(Op.getOperand(1), KnownZero2, KnownOne2, Depth+1); computeKnownBits(Op.getOperand(1), KnownZero2, KnownOne2, Depth+1);
KnownZeroOut = std::min(KnownZeroOut, KnownZeroHigh = std::min(KnownZeroHigh,
KnownZero2.countLeadingOnes());
KnownZeroLow = std::min(KnownZeroLow,
KnownZero2.countTrailingOnes()); KnownZero2.countTrailingOnes());
if (Op.getOpcode() == ISD::ADD) { if (Op.getOpcode() == ISD::ADD) {
KnownZero |= APInt::getLowBitsSet(BitWidth, KnownZeroOut); KnownZero |= APInt::getLowBitsSet(BitWidth, KnownZeroLow);
if (KnownZeroHigh > 1)
KnownZero |= APInt::getHighBitsSet(BitWidth, KnownZeroHigh - 1);
break; break;
} }
@@ -2372,8 +2381,8 @@ void SelectionDAG::computeKnownBits(SDValue Op, APInt &KnownZero,
// information if we know (at least) that the low two bits are clear. We // information if we know (at least) that the low two bits are clear. We
// then return to the caller that the low bit is unknown but that other bits // then return to the caller that the low bit is unknown but that other bits
// are known zero. // are known zero.
if (KnownZeroOut >= 2) // ADDE if (KnownZeroLow >= 2) // ADDE
KnownZero |= APInt::getBitsSet(BitWidth, 1, KnownZeroOut); KnownZero |= APInt::getBitsSet(BitWidth, 1, KnownZeroLow);
break; break;
} }
case ISD::SREM: case ISD::SREM:

10
test/CodeGen/AArch64/aarch64-dynamic-stack-layout.ll
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@@ -255,7 +255,7 @@ entry:
; CHECK: ubfx x9, x0, #0, #32 ; CHECK: ubfx x9, x0, #0, #32
; CHECK: lsl x9, x9, #2 ; CHECK: lsl x9, x9, #2
; CHECK: add x9, x9, #15 ; CHECK: add x9, x9, #15
; CHECK: and x9, x9, #0xfffffffffffffff0 ; CHECK: and x9, x9, #0x7fffffff0
; CHECK: mov x10, sp ; CHECK: mov x10, sp
; CHECK: sub x[[VLASPTMP:[0-9]+]], x10, x9 ; CHECK: sub x[[VLASPTMP:[0-9]+]], x10, x9
; CHECK: mov sp, x[[VLASPTMP]] ; CHECK: mov sp, x[[VLASPTMP]]
@@ -302,7 +302,7 @@ entry:
; CHECK: ubfx x9, x0, #0, #32 ; CHECK: ubfx x9, x0, #0, #32
; CHECK: lsl x9, x9, #2 ; CHECK: lsl x9, x9, #2
; CHECK: add x9, x9, #15 ; CHECK: add x9, x9, #15
; CHECK: and x9, x9, #0xfffffffffffffff0 ; CHECK: and x9, x9, #0x7fffffff0
; CHECK: mov x10, sp ; CHECK: mov x10, sp
; CHECK: sub x[[VLASPTMP:[0-9]+]], x10, x9 ; CHECK: sub x[[VLASPTMP:[0-9]+]], x10, x9
; CHECK: mov sp, x[[VLASPTMP]] ; CHECK: mov sp, x[[VLASPTMP]]
@@ -364,7 +364,7 @@ entry:
; CHECK: ubfx x9, x0, #0, #32 ; CHECK: ubfx x9, x0, #0, #32
; CHECK: lsl x9, x9, #2 ; CHECK: lsl x9, x9, #2
; CHECK: add x9, x9, #15 ; CHECK: add x9, x9, #15
; CHECK: and x9, x9, #0xfffffffffffffff0 ; CHECK: and x9, x9, #0x7fffffff0
; CHECK: mov x10, sp ; CHECK: mov x10, sp
; CHECK: sub x[[VLASPTMP:[0-9]+]], x10, x9 ; CHECK: sub x[[VLASPTMP:[0-9]+]], x10, x9
; CHECK: mov sp, x[[VLASPTMP]] ; CHECK: mov sp, x[[VLASPTMP]]
@@ -417,7 +417,7 @@ entry:
; CHECK: ubfx x9, x0, #0, #32 ; CHECK: ubfx x9, x0, #0, #32
; CHECK: lsl x9, x9, #2 ; CHECK: lsl x9, x9, #2
; CHECK: add x9, x9, #15 ; CHECK: add x9, x9, #15
; CHECK: and x9, x9, #0xfffffffffffffff0 ; CHECK: and x9, x9, #0x7fffffff0
; CHECK: mov x10, sp ; CHECK: mov x10, sp
; CHECK: sub x[[VLASPTMP:[0-9]+]], x10, x9 ; CHECK: sub x[[VLASPTMP:[0-9]+]], x10, x9
; CHECK: mov sp, x[[VLASPTMP]] ; CHECK: mov sp, x[[VLASPTMP]]
@@ -468,7 +468,7 @@ entry:
; CHECK: ubfx x9, x0, #0, #32 ; CHECK: ubfx x9, x0, #0, #32
; CHECK: lsl x9, x9, #2 ; CHECK: lsl x9, x9, #2
; CHECK: add x9, x9, #15 ; CHECK: add x9, x9, #15
; CHECK: and x9, x9, #0xfffffffffffffff0 ; CHECK: and x9, x9, #0x7fffffff0
; CHECK: mov x10, sp ; CHECK: mov x10, sp
; CHECK: sub x[[VLASPTMP:[0-9]+]], x10, x9 ; CHECK: sub x[[VLASPTMP:[0-9]+]], x10, x9
; CHECK: mov sp, x[[VLASPTMP]] ; CHECK: mov sp, x[[VLASPTMP]]

5
test/CodeGen/X86/win64_frame.ll
View File

@@ -100,8 +100,9 @@ define i32 @f8(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) "no-frame-pointer-elim"="
alloca i32, i32 %a alloca i32, i32 %a
; CHECK: movl %ecx, %eax ; CHECK: movl %ecx, %eax
; CHECK: leaq 15(,%rax,4), %rax ; CHECK: leaq 15(,%rax,4), %rcx
; CHECK: andq $-16, %rax ; CHECK: movabsq $34359738352, %rax
; CHECK: andq %rcx, %rax
; CHECK: callq __chkstk ; CHECK: callq __chkstk
; CHECK: subq %rax, %rsp ; CHECK: subq %rax, %rsp