Typo.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231547 91177308-0d34-0410-b5e6-96231b3b80d8

include/llvm/Analysis/TargetLibraryInfo.h

@@ -133,7 +133,7 @@ public:
     return Impl->getLibFunc(funcName, F);
   }
 
-  /// \brief Tests wether a library function is available.
+  /// \brief Tests whether a library function is available.
   bool has(LibFunc::Func F) const {
     return Impl->getState(F) != TargetLibraryInfoImpl::Unavailable;
   }

include/llvm/DebugInfo/DWARF/DWARFFormValue.h

@@ -63,7 +63,7 @@ public:
   /// The passed DWARFUnit is allowed to be nullptr, in which
   /// case no relocation processing will be performed and some
   /// kind of forms that depend on Unit information are disallowed.
-  /// \returns wether the extraction succeeded.
+  /// \returns whether the extraction succeeded.
   bool extractValue(DataExtractor data, uint32_t *offset_ptr,
                     const DWARFUnit *u);
   bool isInlinedCStr() const {

lib/Target/AArch64/AArch64ISelDAGToDAG.cpp

@@ -299,7 +299,7 @@ static AArch64_AM::ShiftExtendType getShiftTypeForNode(SDValue N) {
   }
 }
 
-/// \brief Determine wether it is worth to fold V into an extended register.
+/// \brief Determine whether it is worth to fold V into an extended register.
 bool AArch64DAGToDAGISel::isWorthFolding(SDValue V) const {
   // it hurts if the value is used at least twice, unless we are optimizing
   // for code size.

lib/Target/X86/X86ISelLowering.cpp

@@ -9020,7 +9020,7 @@ static SDValue lowerVectorShuffleAsLanePermuteAndBlend(SDLoc DL, MVT VT,
   int LaneSize = Mask.size() / 2;
 
   // If there are only inputs from one 128-bit lane, splitting will in fact be
-  // less expensive. The flags track wether the given lane contains an element
+  // less expensive. The flags track whether the given lane contains an element
   // that crosses to another lane.
   bool LaneCrossing[2] = {false, false};
   for (int i = 0, Size = Mask.size(); i < Size; ++i)