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Covert this test to .s form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117684 91177308-0d34-0410-b5e6-96231b3b80d8
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Owen Anderson
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@ -1,122 +0,0 @@
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; RUN: llc -show-mc-encoding -march=arm -mcpu=cortex-a8 -mattr=+neon < %s | FileCheck %s
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define <2 x i32> @vcvt_f32tos32(<2 x float>* %A) nounwind {
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%tmp1 = load <2 x float>* %A
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; CHECK: vcvt.s32.f32 d16, d16 @ encoding: [0x20,0x07,0xfb,0xf3]
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%tmp2 = fptosi <2 x float> %tmp1 to <2 x i32>
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ret <2 x i32> %tmp2
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}
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define <2 x i32> @vcvt_f32tou32(<2 x float>* %A) nounwind {
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%tmp1 = load <2 x float>* %A
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; CHECK: vcvt.u32.f32 d16, d16 @ encoding: [0xa0,0x07,0xfb,0xf3]
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%tmp2 = fptoui <2 x float> %tmp1 to <2 x i32>
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ret <2 x i32> %tmp2
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}
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define <2 x float> @vcvt_s32tof32(<2 x i32>* %A) nounwind {
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%tmp1 = load <2 x i32>* %A
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; CHECK: vcvt.f32.s32 d16, d16 @ encoding: [0x20,0x06,0xfb,0xf3]
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%tmp2 = sitofp <2 x i32> %tmp1 to <2 x float>
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ret <2 x float> %tmp2
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}
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define <2 x float> @vcvt_u32tof32(<2 x i32>* %A) nounwind {
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%tmp1 = load <2 x i32>* %A
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; CHECK: vcvt.f32.u32 d16, d16 @ encoding: [0xa0,0x06,0xfb,0xf3]
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%tmp2 = uitofp <2 x i32> %tmp1 to <2 x float>
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ret <2 x float> %tmp2
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}
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define <4 x i32> @vcvtQ_f32tos32(<4 x float>* %A) nounwind {
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%tmp1 = load <4 x float>* %A
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; CHECK: vcvt.s32.f32 q8, q8 @ encoding: [0x60,0x07,0xfb,0xf3]
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%tmp2 = fptosi <4 x float> %tmp1 to <4 x i32>
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ret <4 x i32> %tmp2
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}
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define <4 x i32> @vcvtQ_f32tou32(<4 x float>* %A) nounwind {
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%tmp1 = load <4 x float>* %A
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; CHECK: vcvt.u32.f32 q8, q8 @ encoding: [0xe0,0x07,0xfb,0xf3]
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%tmp2 = fptoui <4 x float> %tmp1 to <4 x i32>
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ret <4 x i32> %tmp2
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}
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define <4 x float> @vcvtQ_s32tof32(<4 x i32>* %A) nounwind {
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%tmp1 = load <4 x i32>* %A
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; CHECK: vcvt.f32.s32 q8, q8 @ encoding: [0x60,0x06,0xfb,0xf3]
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%tmp2 = sitofp <4 x i32> %tmp1 to <4 x float>
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ret <4 x float> %tmp2
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}
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define <4 x float> @vcvtQ_u32tof32(<4 x i32>* %A) nounwind {
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%tmp1 = load <4 x i32>* %A
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; CHECK: vcvt.f32.u32 q8, q8 @ encoding: [0xe0,0x06,0xfb,0xf3]
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%tmp2 = uitofp <4 x i32> %tmp1 to <4 x float>
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ret <4 x float> %tmp2
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}
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define <2 x i32> @vcvt_n_f32tos32(<2 x float>* %A) nounwind {
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%tmp1 = load <2 x float>* %A
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; CHECK: vcvt.s32.f32 d16, d16, #1 @ encoding: [0x30,0x0f,0xff,0xf2
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%tmp2 = call <2 x i32> @llvm.arm.neon.vcvtfp2fxs.v2i32.v2f32(<2 x float> %tmp1, i32 1)
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ret <2 x i32> %tmp2
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}
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define <2 x i32> @vcvt_n_f32tou32(<2 x float>* %A) nounwind {
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%tmp1 = load <2 x float>* %A
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; CHECK: vcvt.u32.f32 d16, d16, #1 @ encoding: [0x30,0x0f,0xff,0xf3]
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%tmp2 = call <2 x i32> @llvm.arm.neon.vcvtfp2fxu.v2i32.v2f32(<2 x float> %tmp1, i32 1)
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ret <2 x i32> %tmp2
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}
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define <2 x float> @vcvt_n_s32tof32(<2 x i32>* %A) nounwind {
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%tmp1 = load <2 x i32>* %A
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; CHECK: vcvt.f32.s32 d16, d16, #1 @ encoding: [0x30,0x0e,0xff,0xf2]
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%tmp2 = call <2 x float> @llvm.arm.neon.vcvtfxs2fp.v2f32.v2i32(<2 x i32> %tmp1, i32 1)
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ret <2 x float> %tmp2
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}
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define <2 x float> @vcvt_n_u32tof32(<2 x i32>* %A) nounwind {
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%tmp1 = load <2 x i32>* %A
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; CHECK: vcvt.f32.u32 d16, d16, #1 @ encoding: [0x30,0x0e,0xff,0xf3]
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%tmp2 = call <2 x float> @llvm.arm.neon.vcvtfxu2fp.v2f32.v2i32(<2 x i32> %tmp1, i32 1)
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ret <2 x float> %tmp2
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}
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declare <2 x i32> @llvm.arm.neon.vcvtfp2fxs.v2i32.v2f32(<2 x float>, i32) nounwind readnone
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declare <2 x i32> @llvm.arm.neon.vcvtfp2fxu.v2i32.v2f32(<2 x float>, i32) nounwind readnone
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declare <2 x float> @llvm.arm.neon.vcvtfxs2fp.v2f32.v2i32(<2 x i32>, i32) nounwind readnone
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declare <2 x float> @llvm.arm.neon.vcvtfxu2fp.v2f32.v2i32(<2 x i32>, i32) nounwind readnone
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define <4 x i32> @vcvtQ_n_f32tos32(<4 x float>* %A) nounwind {
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%tmp1 = load <4 x float>* %A
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; CHECK: vcvt.s32.f32 q8, q8, #1 @ encoding: [0x70,0x0f,0xff,0xf2]
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%tmp2 = call <4 x i32> @llvm.arm.neon.vcvtfp2fxs.v4i32.v4f32(<4 x float> %tmp1, i32 1)
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ret <4 x i32> %tmp2
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}
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define <4 x i32> @vcvtQ_n_f32tou32(<4 x float>* %A) nounwind {
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%tmp1 = load <4 x float>* %A
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%tmp2 = call <4 x i32> @llvm.arm.neon.vcvtfp2fxu.v4i32.v4f32(<4 x float> %tmp1, i32 1)
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ret <4 x i32> %tmp2
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}
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define <4 x float> @vcvtQ_n_s32tof32(<4 x i32>* %A) nounwind {
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%tmp1 = load <4 x i32>* %A
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; CHECK: vcvt.u32.f32 q8, q8, #1 @ encoding: [0x70,0x0f,0xff,0xf3]
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%tmp2 = call <4 x float> @llvm.arm.neon.vcvtfxs2fp.v4f32.v4i32(<4 x i32> %tmp1, i32 1)
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ret <4 x float> %tmp2
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}
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define <4 x float> @vcvtQ_n_u32tof32(<4 x i32>* %A) nounwind {
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%tmp1 = load <4 x i32>* %A
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; CHECK: vcvt.f32.u32 q8, q8, #1 @ encoding: [0x70,0x0e,0xff,0xf3]
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%tmp2 = call <4 x float> @llvm.arm.neon.vcvtfxu2fp.v4f32.v4i32(<4 x i32> %tmp1, i32 1)
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ret <4 x float> %tmp2
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}
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declare <4 x i32> @llvm.arm.neon.vcvtfp2fxs.v4i32.v4f32(<4 x float>, i32) nounwind readnone
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declare <4 x i32> @llvm.arm.neon.vcvtfp2fxu.v4i32.v4f32(<4 x float>, i32) nounwind readnone
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declare <4 x float> @llvm.arm.neon.vcvtfxs2fp.v4f32.v4i32(<4 x i32>, i32) nounwind readnone
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declare <4 x float> @llvm.arm.neon.vcvtfxu2fp.v4f32.v4i32(<4 x i32>, i32) nounwind readnone
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34
test/MC/ARM/neon-convert-encoding.s
Normal file
34
test/MC/ARM/neon-convert-encoding.s
Normal file
@ -0,0 +1,34 @@
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// RUN: llvm-mc -triple arm-unknown-unkown -show-encoding < %s | FileCheck %s
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// CHECK: vcvt.s32.f32 d16, d16 @ encoding: [0x20,0x07,0xfb,0xf3]
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vcvt.s32.f32 d16, d16
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// CHECK: vcvt.u32.f32 d16, d16 @ encoding: [0xa0,0x07,0xfb,0xf3]
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vcvt.u32.f32 d16, d16
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// CHECK: vcvt.f32.s32 d16, d16 @ encoding: [0x20,0x06,0xfb,0xf3]
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vcvt.f32.s32 d16, d16
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// CHECK: vcvt.f32.u32 d16, d16 @ encoding: [0xa0,0x06,0xfb,0xf3]
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vcvt.f32.u32 d16, d16
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// CHECK: vcvt.s32.f32 q8, q8 @ encoding: [0x60,0x07,0xfb,0xf3]
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vcvt.s32.f32 q8, q8
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// CHECK: vcvt.u32.f32 q8, q8 @ encoding: [0xe0,0x07,0xfb,0xf3]
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vcvt.u32.f32 q8, q8
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// CHECK: vcvt.f32.s32 q8, q8 @ encoding: [0x60,0x06,0xfb,0xf3]
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vcvt.f32.s32 q8, q8
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// CHECK: vcvt.f32.u32 q8, q8 @ encoding: [0xe0,0x06,0xfb,0xf3]
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vcvt.f32.u32 q8, q8
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// CHECK: vcvt.s32.f32 d16, d16, #1 @ encoding: [0x30,0x0f,0xff,0xf2]
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vcvt.s32.f32 d16, d16, #1
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// CHECK: vcvt.u32.f32 d16, d16, #1 @ encoding: [0x30,0x0f,0xff,0xf3]
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vcvt.u32.f32 d16, d16, #1
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// CHECK: vcvt.f32.s32 d16, d16, #1 @ encoding: [0x30,0x0e,0xff,0xf2]
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vcvt.f32.s32 d16, d16, #1
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// CHECK: vcvt.f32.u32 d16, d16, #1 @ encoding: [0x30,0x0e,0xff,0xf3]
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vcvt.f32.u32 d16, d16, #1
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// CHECK: vcvt.s32.f32 q8, q8, #1 @ encoding: [0x70,0x0f,0xff,0xf2]
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vcvt.s32.f32 q8, q8, #1
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// CHECK: vcvt.u32.f32 q8, q8, #1 @ encoding: [0x70,0x0f,0xff,0xf3]
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vcvt.u32.f32 q8, q8, #1
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// CHECK: vcvt.f32.s32 q8, q8, #1 @ encoding: [0x70,0x0e,0xff,0xf2]
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vcvt.f32.s32 q8, q8, #1
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// CHECK: vcvt.f32.u32 q8, q8, #1 @ encoding: [0x70,0x0e,0xff,0xf3]
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vcvt.f32.u32 q8, q8, #1
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