6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-06-13 04:38:24 +00:00
Code Issues Projects Releases Wiki Activity

Fix an over-constrained assertion in MachineFunction::addLiveIn.

Browse Source 
The assertion was checking that the virtual register VReg used to represent the
physical register PReg uses the same register class as the one passed to
MachineFunction::addLiveIn.
This is over-constraining because it is sufficient to check that the register
class of VReg (VRegRC) is a subclass of the register class of PReg (PRegRC) and
that VRegRC contains PReg.
Indeed, if VReg gets constrained because of some operation constraints
between two calls of MachineFunction::addLiveIn, the original assertion
cannot match.

This fixes <rdar://problem/15633429>. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197097 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Quentin Colombet
2013-12-12 00:15:47 +00:00
parent 76eb77dd52
commit b0f8afd43c
2 changed files with 34 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

11
lib/CodeGen/MachineFunction.cpp
View File

@ -425,7 +425,16 @@ unsigned MachineFunction::addLiveIn(unsigned PReg,
MachineRegisterInfo &MRI = getRegInfo();
unsigned VReg = MRI.getLiveInVirtReg(PReg);
if (VReg) {
assert(MRI.getRegClass(VReg) == RC && "Register class mismatch!");
const TargetRegisterClass *VRegRC = MRI.getRegClass(VReg);
(void)VRegRC;
// A physical register can be added several times.
// Between two calls, the register class of the related virtual register
// may have been constrained to match some operation constraints.
// In that case, check that the current register class includes the
// physical register and is a sub class of the specified RC.
assert((VRegRC == RC || (VRegRC->contains(PReg) &&
RC->hasSubClassEq(VRegRC))) &&
"Register class mismatch!");
return VReg;
}
VReg = MRI.createVirtualRegister(RC);