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[PowerPC] Add a full condition code register to make the "cc" clobber work

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gcc inline asm supports specifying "cc" as a clobber of all condition
registers. Add just enough modeling of the full register to make this work.
Fixed PR19326.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205630 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Hal Finkel
2014-04-04 15:15:57 +00:00
parent dc404fff12
commit b12c642bbf
2 changed files with 82 additions and 0 deletions
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70
test/CodeGen/PowerPC/cc.ll Normal file
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; RUN: llc -mcpu=pwr7 < %s | FileCheck %s
target datalayout = "E-m:e-i64:64-n32:64"
target triple = "powerpc64-unknown-linux-gnu"
define i64 @test1(i64 %a, i64 %b) {
entry:
%c = icmp eq i64 %a, %b
br label %foo
foo:
call { i64, i64 } asm sideeffect "sc", "={r0},={r3},{r0},~{cr0},~{cr1},~{cr2},~{cr3},~{cr4},~{cr5},~{cr6},~{cr7}" (i64 %a)
br i1 %c, label %bar, label %end
bar:
ret i64 %b
end:
ret i64 %a
; CHECK-LABEL: @test1
; CHECK: mfcr [[REG1:[0-9]+]]
; CHECK-DAG: cmpd
; CHECK-DAG: mfocrf [[REG2:[0-9]+]],
; CHECK-DAG: stw [[REG1]], 8(1)
; CHECK-DAG: stw [[REG2]], -4(1)
; CHECK: sc
; CHECK: lwz [[REG3:[0-9]+]], -4(1)
; CHECK: mtocrf 128, [[REG3]]
; CHECK: lwz [[REG4:[0-9]+]], 8(1)
; CHECK-DAG: mtocrf 32, [[REG4]]
; CHECK-DAG: mtocrf 16, [[REG4]]
; CHECK-DAG: mtocrf 8, [[REG4]]
; CHECK: blr
}
define i64 @test2(i64 %a, i64 %b) {
entry:
%c = icmp eq i64 %a, %b
br label %foo
foo:
call { i64, i64 } asm sideeffect "sc", "={r0},={r3},{r0},~{cc}" (i64 %a)
br i1 %c, label %bar, label %end
bar:
ret i64 %b
end:
ret i64 %a
; CHECK-LABEL: @test2
; CHECK: mfcr [[REG1:[0-9]+]]
; CHECK-DAG: cmpd
; CHECK-DAG: mfocrf [[REG2:[0-9]+]],
; CHECK-DAG: stw [[REG1]], 8(1)
; CHECK-DAG: stw [[REG2]], -4(1)
; CHECK: sc
; CHECK: lwz [[REG3:[0-9]+]], -4(1)
; CHECK: mtocrf 128, [[REG3]]
; CHECK: lwz [[REG4:[0-9]+]], 8(1)
; CHECK-DAG: mtocrf 32, [[REG4]]
; CHECK-DAG: mtocrf 16, [[REG4]]
; CHECK-DAG: mtocrf 8, [[REG4]]
; CHECK: blr
}