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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-27 13:30:05 +00:00
Made a fix so that you can print out MachineInstrs that belong to a MachineBasicBlock that is not yet attached to a MachineFunction. This change includes changing the third operand (TargetMachine) to a pointer for the MachineInstr::print function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14389 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -308,7 +308,13 @@ public:
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// code.' It's not clear where the duplication is.
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assert(hasAllocatedReg() && "This operand cannot have a register number!");
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regNum = Reg;
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}
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}
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void setValueReg(Value *val) {
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assert(getVRegValueOrNull() != 0 && "Original operand must of type Value*");
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contents.value = val;
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}
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void setImmedValue(int immVal) {
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assert(isImmediate() && "Wrong MachineOperand mutator");
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contents.immedVal = immVal;
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@ -465,7 +471,7 @@ public:
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//
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// Debugging support
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//
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void print(std::ostream &OS, const TargetMachine &TM) const;
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void print(std::ostream &OS, const TargetMachine *TM) const;
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void dump() const;
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friend std::ostream& operator<<(std::ostream& os, const MachineInstr& minstr);
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@ -179,7 +179,7 @@ bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
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for (MachineBasicBlock::iterator mii = mbbi->begin(),
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mie = mbbi->end(); mii != mie; ++mii) {
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std::cerr << getInstructionIndex(mii) << '\t';
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mii->print(std::cerr, *tm_);
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mii->print(std::cerr, tm_);
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}
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});
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@ -427,7 +427,7 @@ void LiveIntervals::computeIntervals()
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const TargetInstrDescriptor& tid =
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tm_->getInstrInfo()->get(mi->getOpcode());
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DEBUG(std::cerr << getInstructionIndex(mi) << "\t";
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mi->print(std::cerr, *tm_));
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mi->print(std::cerr, tm_));
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// handle implicit defs
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for (const unsigned* id = tid.ImplicitDefs; *id; ++id)
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@ -467,7 +467,7 @@ void LiveIntervals::joinIntervals()
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mi != mie; ++mi) {
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const TargetInstrDescriptor& tid = tii.get(mi->getOpcode());
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DEBUG(std::cerr << getInstructionIndex(mi) << '\t';
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mi->print(std::cerr, *tm_););
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mi->print(std::cerr, tm_););
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// we only join virtual registers with allocatable
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// physical registers since we do not have liveness information
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@ -105,6 +105,6 @@ void MachineBasicBlock::print(std::ostream &OS) const
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<< ", LLVM BB @" << (const void*) LBB << "):\n";
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for (const_iterator I = begin(); I != end(); ++I) {
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OS << "\t";
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I->print(OS, getParent()->getTarget());
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I->print(OS, &getParent()->getTarget());
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}
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}
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@ -235,8 +235,14 @@ static inline void OutputReg(std::ostream &os, unsigned RegNo,
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}
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static void print(const MachineOperand &MO, std::ostream &OS,
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const TargetMachine &TM) {
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const MRegisterInfo *MRI = TM.getRegisterInfo();
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const TargetMachine *TM) {
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const MRegisterInfo *MRI = 0;
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if(TM)
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MRI = TM->getRegisterInfo();
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bool CloseParen = true;
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if (MO.isHiBits32())
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OS << "%lm(";
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@ -313,7 +319,7 @@ static void print(const MachineOperand &MO, std::ostream &OS,
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OS << ")";
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}
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void MachineInstr::print(std::ostream &OS, const TargetMachine &TM) const {
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void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const {
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unsigned StartOp = 0;
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// Specialize printing if op#0 is definition
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@ -322,7 +328,11 @@ void MachineInstr::print(std::ostream &OS, const TargetMachine &TM) const {
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OS << " = ";
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++StartOp; // Don't print this operand again!
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}
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OS << TM.getInstrInfo()->getName(getOpcode());
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//Must check if Target machine is not null because machine BB could not
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//be attached to a Machine function yet
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if(TM)
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OS << TM->getInstrInfo()->getName(getOpcode());
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for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
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const MachineOperand& mop = getOperand(i);
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@ -361,7 +371,10 @@ std::ostream &operator<<(std::ostream &os, const MachineInstr &MI) {
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// info for the instruction.
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if (const MachineBasicBlock *MBB = MI.getParent()) {
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const MachineFunction *MF = MBB->getParent();
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MI.print(os, MF->getTarget());
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if(MF)
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MI.print(os, &MF->getTarget());
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else
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MI.print(os, 0);
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return os;
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}
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@ -177,7 +177,7 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
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unsigned virtualReg = (unsigned) op.getReg();
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DEBUG(std::cerr << "op: " << op << "\n");
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DEBUG(std::cerr << "\t inst[" << i << "]: ";
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MI->print(std::cerr, *TM));
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MI->print(std::cerr, TM));
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// make sure the same virtual register maps to the same physical
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// register in any given instruction
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@ -98,7 +98,7 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
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++numTwoAddressInstrs;
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DEBUG(std::cerr << '\t'; mi->print(std::cerr, TM));
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DEBUG(std::cerr << '\t'; mi->print(std::cerr, &TM));
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assert(mi->getOperand(1).isRegister() &&
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mi->getOperand(1).getReg() &&
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@ -140,7 +140,7 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
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MachineBasicBlock::iterator prevMi = prior(mi);
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DEBUG(std::cerr << "\t\tprepend:\t";
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prevMi->print(std::cerr, TM));
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prevMi->print(std::cerr, &TM));
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if (LV) {
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// update live variables for regA
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@ -170,7 +170,7 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
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mi->RemoveOperand(1);
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DEBUG(std::cerr << "\t\trewrite to:\t";
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mi->print(std::cerr, TM));
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mi->print(std::cerr, &TM));
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}
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}
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@ -149,7 +149,7 @@ namespace {
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mf.getSSARegMap()->getRegClass(virtReg));
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loaded[virtReg] = true;
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DEBUG(std::cerr << '\t';
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prior(mii)->print(std::cerr, tm));
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prior(mii)->print(std::cerr, &tm));
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++numLoads;
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}
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if (mop.isDef() &&
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@ -165,7 +165,7 @@ namespace {
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mii->SetMachineOperandReg(i, physReg);
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}
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}
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DEBUG(std::cerr << '\t'; mii->print(std::cerr, tm));
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DEBUG(std::cerr << '\t'; mii->print(std::cerr, &tm));
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loaded.clear();
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}
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}
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@ -231,9 +231,9 @@ namespace {
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mri_->getRegClass(physReg));
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++numStores;
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DEBUG(std::cerr << "added: ";
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prior(nextLastRef)->print(std::cerr, *tm_);
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prior(nextLastRef)->print(std::cerr, tm_);
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std::cerr << "after: ";
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lastDef->print(std::cerr, *tm_));
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lastDef->print(std::cerr, tm_));
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lastDef_[virtReg] = 0;
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}
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p2vMap_[physReg] = 0;
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@ -263,7 +263,7 @@ namespace {
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mri_->getRegClass(physReg));
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++numLoads;
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DEBUG(std::cerr << "added: ";
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prior(mii)->print(std::cerr, *tm_));
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prior(mii)->print(std::cerr, tm_));
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lastDef_[virtReg] = mii;
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}
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}
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@ -339,7 +339,7 @@ namespace {
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}
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}
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DEBUG(std::cerr << '\t'; mii->print(std::cerr, *tm_));
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DEBUG(std::cerr << '\t'; mii->print(std::cerr, tm_));
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}
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for (unsigned i = 1, e = p2vMap_.size(); i != e; ++i)
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@ -194,7 +194,7 @@ bool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) {
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++NumFP; // Keep track of # of pseudo instrs
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DEBUG(std::cerr << "\nFPInst:\t";
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MI->print(std::cerr, MF.getTarget()));
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MI->print(std::cerr, &(MF.getTarget())));
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// Get dead variables list now because the MI pointer may be deleted as part
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// of processing!
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@ -242,7 +242,7 @@ bool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) {
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// Rewind to first instruction newly inserted.
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while (Start != BB.begin() && prior(Start) != PrevI) --Start;
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std::cerr << "Inserted instructions:\n\t";
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Start->print(std::cerr, MF.getTarget());
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Start->print(std::cerr, &MF.getTarget());
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while (++Start != next(I));
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}
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dumpStack();
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@ -936,7 +936,7 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
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return;
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}
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default:
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O << "\tUNKNOWN FORM:\t\t-"; MI->print(O, TM); break;
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O << "\tUNKNOWN FORM:\t\t-"; MI->print(O, &TM); break;
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}
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}
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@ -936,7 +936,7 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
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return;
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}
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default:
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O << "\tUNKNOWN FORM:\t\t-"; MI->print(O, TM); break;
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O << "\tUNKNOWN FORM:\t\t-"; MI->print(O, &TM); break;
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}
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}
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@ -194,7 +194,7 @@ bool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) {
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++NumFP; // Keep track of # of pseudo instrs
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DEBUG(std::cerr << "\nFPInst:\t";
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MI->print(std::cerr, MF.getTarget()));
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MI->print(std::cerr, &(MF.getTarget())));
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// Get dead variables list now because the MI pointer may be deleted as part
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// of processing!
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@ -242,7 +242,7 @@ bool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) {
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// Rewind to first instruction newly inserted.
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while (Start != BB.begin() && prior(Start) != PrevI) --Start;
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std::cerr << "Inserted instructions:\n\t";
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Start->print(std::cerr, MF.getTarget());
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Start->print(std::cerr, &MF.getTarget());
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while (++Start != next(I));
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}
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dumpStack();
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