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Made a fix so that you can print out MachineInstrs that belong to a MachineBasicBlock that is not yet attached to a MachineFunction. This change includes changing the third operand (TargetMachine) to a pointer for the MachineInstr::print function.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14389 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tanya Lattner 2004-06-25 00:13:11 +00:00
parent 32b588039e
commit b140762a45
11 changed files with 46 additions and 27 deletions
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8
include/llvm/CodeGen/MachineInstr.h
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@ -309,6 +309,12 @@ public:
assert(hasAllocatedReg() && "This operand cannot have a register number!"); assert(hasAllocatedReg() && "This operand cannot have a register number!");
regNum = Reg; regNum = Reg;
} }
void setValueReg(Value *val) {
assert(getVRegValueOrNull() != 0 && "Original operand must of type Value*");
contents.value = val;
}
void setImmedValue(int immVal) { void setImmedValue(int immVal) {
assert(isImmediate() && "Wrong MachineOperand mutator"); assert(isImmediate() && "Wrong MachineOperand mutator");
contents.immedVal = immVal; contents.immedVal = immVal;
@ -465,7 +471,7 @@ public:
// //
// Debugging support // Debugging support
// //
void print(std::ostream &OS, const TargetMachine &TM) const; void print(std::ostream &OS, const TargetMachine *TM) const;
void dump() const; void dump() const;
friend std::ostream& operator<<(std::ostream& os, const MachineInstr& minstr); friend std::ostream& operator<<(std::ostream& os, const MachineInstr& minstr);

6
lib/CodeGen/LiveIntervalAnalysis.cpp
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@ -179,7 +179,7 @@ bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
for (MachineBasicBlock::iterator mii = mbbi->begin(), for (MachineBasicBlock::iterator mii = mbbi->begin(),
mie = mbbi->end(); mii != mie; ++mii) { mie = mbbi->end(); mii != mie; ++mii) {
std::cerr << getInstructionIndex(mii) << '\t'; std::cerr << getInstructionIndex(mii) << '\t';
mii->print(std::cerr, *tm_); mii->print(std::cerr, tm_);
} }
}); });
@ -427,7 +427,7 @@ void LiveIntervals::computeIntervals()
const TargetInstrDescriptor& tid = const TargetInstrDescriptor& tid =
tm_->getInstrInfo()->get(mi->getOpcode()); tm_->getInstrInfo()->get(mi->getOpcode());
DEBUG(std::cerr << getInstructionIndex(mi) << "\t"; DEBUG(std::cerr << getInstructionIndex(mi) << "\t";
mi->print(std::cerr, *tm_)); mi->print(std::cerr, tm_));
// handle implicit defs // handle implicit defs
for (const unsigned* id = tid.ImplicitDefs; *id; ++id) for (const unsigned* id = tid.ImplicitDefs; *id; ++id)
@ -467,7 +467,7 @@ void LiveIntervals::joinIntervals()
mi != mie; ++mi) { mi != mie; ++mi) {
const TargetInstrDescriptor& tid = tii.get(mi->getOpcode()); const TargetInstrDescriptor& tid = tii.get(mi->getOpcode());
DEBUG(std::cerr << getInstructionIndex(mi) << '\t'; DEBUG(std::cerr << getInstructionIndex(mi) << '\t';
mi->print(std::cerr, *tm_);); mi->print(std::cerr, tm_););
// we only join virtual registers with allocatable // we only join virtual registers with allocatable
// physical registers since we do not have liveness information // physical registers since we do not have liveness information

2
lib/CodeGen/MachineBasicBlock.cpp
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@ -105,6 +105,6 @@ void MachineBasicBlock::print(std::ostream &OS) const
<< ", LLVM BB @" << (const void*) LBB << "):\n"; << ", LLVM BB @" << (const void*) LBB << "):\n";
for (const_iterator I = begin(); I != end(); ++I) { for (const_iterator I = begin(); I != end(); ++I) {
OS << "\t"; OS << "\t";
I->print(OS, getParent()->getTarget()); I->print(OS, &getParent()->getTarget());
} }
} }

23
lib/CodeGen/MachineInstr.cpp
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@ -235,8 +235,14 @@ static inline void OutputReg(std::ostream &os, unsigned RegNo,
} }
static void print(const MachineOperand &MO, std::ostream &OS, static void print(const MachineOperand &MO, std::ostream &OS,
const TargetMachine &TM) { const TargetMachine *TM) {
const MRegisterInfo *MRI = TM.getRegisterInfo();
const MRegisterInfo *MRI = 0;
if(TM)
MRI = TM->getRegisterInfo();
bool CloseParen = true; bool CloseParen = true;
if (MO.isHiBits32()) if (MO.isHiBits32())
OS << "%lm("; OS << "%lm(";
@ -313,7 +319,7 @@ static void print(const MachineOperand &MO, std::ostream &OS,
OS << ")"; OS << ")";
} }
void MachineInstr::print(std::ostream &OS, const TargetMachine &TM) const { void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const {
unsigned StartOp = 0; unsigned StartOp = 0;
// Specialize printing if op#0 is definition // Specialize printing if op#0 is definition
@ -322,7 +328,11 @@ void MachineInstr::print(std::ostream &OS, const TargetMachine &TM) const {
OS << " = "; OS << " = ";
++StartOp; // Don't print this operand again! ++StartOp; // Don't print this operand again!
} }
OS << TM.getInstrInfo()->getName(getOpcode());
//Must check if Target machine is not null because machine BB could not
//be attached to a Machine function yet
if(TM)
OS << TM->getInstrInfo()->getName(getOpcode());
for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) { for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
const MachineOperand& mop = getOperand(i); const MachineOperand& mop = getOperand(i);
@ -361,7 +371,10 @@ std::ostream &operator<<(std::ostream &os, const MachineInstr &MI) {
// info for the instruction. // info for the instruction.
if (const MachineBasicBlock *MBB = MI.getParent()) { if (const MachineBasicBlock *MBB = MI.getParent()) {
const MachineFunction *MF = MBB->getParent(); const MachineFunction *MF = MBB->getParent();
MI.print(os, MF->getTarget()); if(MF)
MI.print(os, &MF->getTarget());
else
MI.print(os, 0);
return os; return os;
} }

2
lib/CodeGen/RegAllocSimple.cpp
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@ -177,7 +177,7 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
unsigned virtualReg = (unsigned) op.getReg(); unsigned virtualReg = (unsigned) op.getReg();
DEBUG(std::cerr << "op: " << op << "\n"); DEBUG(std::cerr << "op: " << op << "\n");
DEBUG(std::cerr << "\t inst[" << i << "]: "; DEBUG(std::cerr << "\t inst[" << i << "]: ";
MI->print(std::cerr, *TM)); MI->print(std::cerr, TM));
// make sure the same virtual register maps to the same physical // make sure the same virtual register maps to the same physical
// register in any given instruction // register in any given instruction

6
lib/CodeGen/TwoAddressInstructionPass.cpp
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@ -98,7 +98,7 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
++numTwoAddressInstrs; ++numTwoAddressInstrs;
DEBUG(std::cerr << '\t'; mi->print(std::cerr, TM)); DEBUG(std::cerr << '\t'; mi->print(std::cerr, &TM));
assert(mi->getOperand(1).isRegister() && assert(mi->getOperand(1).isRegister() &&
mi->getOperand(1).getReg() && mi->getOperand(1).getReg() &&
@ -140,7 +140,7 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
MachineBasicBlock::iterator prevMi = prior(mi); MachineBasicBlock::iterator prevMi = prior(mi);
DEBUG(std::cerr << "\t\tprepend:\t"; DEBUG(std::cerr << "\t\tprepend:\t";
prevMi->print(std::cerr, TM)); prevMi->print(std::cerr, &TM));
if (LV) { if (LV) {
// update live variables for regA // update live variables for regA
@ -170,7 +170,7 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
mi->RemoveOperand(1); mi->RemoveOperand(1);
DEBUG(std::cerr << "\t\trewrite to:\t"; DEBUG(std::cerr << "\t\trewrite to:\t";
mi->print(std::cerr, TM)); mi->print(std::cerr, &TM));
} }
} }

12
lib/CodeGen/VirtRegMap.cpp
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@ -149,7 +149,7 @@ namespace {
mf.getSSARegMap()->getRegClass(virtReg)); mf.getSSARegMap()->getRegClass(virtReg));
loaded[virtReg] = true; loaded[virtReg] = true;
DEBUG(std::cerr << '\t'; DEBUG(std::cerr << '\t';
prior(mii)->print(std::cerr, tm)); prior(mii)->print(std::cerr, &tm));
++numLoads; ++numLoads;
} }
if (mop.isDef() && if (mop.isDef() &&
@ -165,7 +165,7 @@ namespace {
mii->SetMachineOperandReg(i, physReg); mii->SetMachineOperandReg(i, physReg);
} }
} }
DEBUG(std::cerr << '\t'; mii->print(std::cerr, tm)); DEBUG(std::cerr << '\t'; mii->print(std::cerr, &tm));
loaded.clear(); loaded.clear();
} }
} }
@ -231,9 +231,9 @@ namespace {
mri_->getRegClass(physReg)); mri_->getRegClass(physReg));
++numStores; ++numStores;
DEBUG(std::cerr << "added: "; DEBUG(std::cerr << "added: ";
prior(nextLastRef)->print(std::cerr, *tm_); prior(nextLastRef)->print(std::cerr, tm_);
std::cerr << "after: "; std::cerr << "after: ";
lastDef->print(std::cerr, *tm_)); lastDef->print(std::cerr, tm_));
lastDef_[virtReg] = 0; lastDef_[virtReg] = 0;
} }
p2vMap_[physReg] = 0; p2vMap_[physReg] = 0;
@ -263,7 +263,7 @@ namespace {
mri_->getRegClass(physReg)); mri_->getRegClass(physReg));
++numLoads; ++numLoads;
DEBUG(std::cerr << "added: "; DEBUG(std::cerr << "added: ";
prior(mii)->print(std::cerr, *tm_)); prior(mii)->print(std::cerr, tm_));
lastDef_[virtReg] = mii; lastDef_[virtReg] = mii;
} }
} }
@ -339,7 +339,7 @@ namespace {
} }
} }
DEBUG(std::cerr << '\t'; mii->print(std::cerr, *tm_)); DEBUG(std::cerr << '\t'; mii->print(std::cerr, tm_));
} }
for (unsigned i = 1, e = p2vMap_.size(); i != e; ++i) for (unsigned i = 1, e = p2vMap_.size(); i != e; ++i)

4
lib/Target/X86/FloatingPoint.cpp
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@ -194,7 +194,7 @@ bool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) {
++NumFP; // Keep track of # of pseudo instrs ++NumFP; // Keep track of # of pseudo instrs
DEBUG(std::cerr << "\nFPInst:\t"; DEBUG(std::cerr << "\nFPInst:\t";
MI->print(std::cerr, MF.getTarget())); MI->print(std::cerr, &(MF.getTarget())));
// Get dead variables list now because the MI pointer may be deleted as part // Get dead variables list now because the MI pointer may be deleted as part
// of processing! // of processing!
@ -242,7 +242,7 @@ bool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) {
// Rewind to first instruction newly inserted. // Rewind to first instruction newly inserted.
while (Start != BB.begin() && prior(Start) != PrevI) --Start; while (Start != BB.begin() && prior(Start) != PrevI) --Start;
std::cerr << "Inserted instructions:\n\t"; std::cerr << "Inserted instructions:\n\t";
Start->print(std::cerr, MF.getTarget()); Start->print(std::cerr, &MF.getTarget());
while (++Start != next(I)); while (++Start != next(I));
} }
dumpStack(); dumpStack();

2
lib/Target/X86/Printer.cpp
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@ -936,7 +936,7 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
return; return;
} }
default: default:
O << "\tUNKNOWN FORM:\t\t-"; MI->print(O, TM); break; O << "\tUNKNOWN FORM:\t\t-"; MI->print(O, &TM); break;
} }
} }

2
lib/Target/X86/X86AsmPrinter.cpp
View File

@ -936,7 +936,7 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
return; return;
} }
default: default:
O << "\tUNKNOWN FORM:\t\t-"; MI->print(O, TM); break; O << "\tUNKNOWN FORM:\t\t-"; MI->print(O, &TM); break;
} }
} }

4
lib/Target/X86/X86FloatingPoint.cpp
View File

@ -194,7 +194,7 @@ bool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) {
++NumFP; // Keep track of # of pseudo instrs ++NumFP; // Keep track of # of pseudo instrs
DEBUG(std::cerr << "\nFPInst:\t"; DEBUG(std::cerr << "\nFPInst:\t";
MI->print(std::cerr, MF.getTarget())); MI->print(std::cerr, &(MF.getTarget())));
// Get dead variables list now because the MI pointer may be deleted as part // Get dead variables list now because the MI pointer may be deleted as part
// of processing! // of processing!
@ -242,7 +242,7 @@ bool FPS::processBasicBlock(MachineFunction &MF, MachineBasicBlock &BB) {
// Rewind to first instruction newly inserted. // Rewind to first instruction newly inserted.
while (Start != BB.begin() && prior(Start) != PrevI) --Start; while (Start != BB.begin() && prior(Start) != PrevI) --Start;
std::cerr << "Inserted instructions:\n\t"; std::cerr << "Inserted instructions:\n\t";
Start->print(std::cerr, MF.getTarget()); Start->print(std::cerr, &MF.getTarget());
while (++Start != next(I)); while (++Start != next(I));
} }
dumpStack(); dumpStack();