From b24b820bd7ddfe118141422f4d0cf378b2c9a6fd Mon Sep 17 00:00:00 2001 From: Jakob Stoklund Olesen Date: Thu, 1 Mar 2012 22:57:32 +0000 Subject: [PATCH] Handle regmasks in Thumb1RegisterInfo::saveScavengerRegister(). This function could have r12 live across a function call when compiling thumb1 code. The test case for this is not included because it is very long. It must provoke emergency spilling near a function call. The behavior is provoked by MultiSource/Applications/JM/lencod, and it triggers an assertion in the scavenger. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151855 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/Thumb1RegisterInfo.cpp | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/lib/Target/ARM/Thumb1RegisterInfo.cpp b/lib/Target/ARM/Thumb1RegisterInfo.cpp index 1613acd7a60..6b8bf0e6398 100644 --- a/lib/Target/ARM/Thumb1RegisterInfo.cpp +++ b/lib/Target/ARM/Thumb1RegisterInfo.cpp @@ -571,6 +571,11 @@ Thumb1RegisterInfo::saveScavengerRegister(MachineBasicBlock &MBB, // If this instruction affects R12, adjust our restore point. for (unsigned i = 0, e = II->getNumOperands(); i != e; ++i) { const MachineOperand &MO = II->getOperand(i); + if (MO.isRegMask() && MO.clobbersPhysReg(ARM::R12)) { + UseMI = II; + done = true; + break; + } if (!MO.isReg() || MO.isUndef() || !MO.getReg() || TargetRegisterInfo::isVirtualRegister(MO.getReg())) continue;