From b29b4dd988c50d5c4a15cd196e7910bf46f30b83 Mon Sep 17 00:00:00 2001 From: Jim Grosbach Date: Tue, 19 Jul 2011 22:45:10 +0000 Subject: [PATCH] Tweak ARM assembly parsing and printing of MSR instruction. The system register spec should be case insensitive. The preferred form for output with mask values of 4, 8, and 12 references APSR rather than CPSR. Update and tidy up tests accordingly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135532 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMInstrInfo.td | 6 +- lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 4 +- lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp | 17 ++++- test/MC/ARM/arm_instructions.s | 39 ----------- test/MC/ARM/basic-arm-instructions.s | 64 +++++++++++++++++++ test/MC/Disassembler/ARM/arm-tests.txt | 4 +- test/MC/Disassembler/ARM/thumb-tests.txt | 2 +- 7 files changed, 86 insertions(+), 50 deletions(-) diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index 23a7c1bfcbf..9a140679a7b 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -3798,8 +3798,7 @@ def MRSsys : ABI<0b0001, (outs GPR:$Rd), (ins), NoItinerary, // operand contains the special register (R Bit) in bit 4 and bits 3-0 contains // the mask with the fields to be accessed in the special register. def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary, - "msr", "\t$mask, $Rn", - [/* For disassembly only; pattern left blank */]> { + "msr", "\t$mask, $Rn", []> { bits<5> mask; bits<4> Rn; @@ -3813,8 +3812,7 @@ def MSR : ABI<0b0001, (outs), (ins msr_mask:$mask, GPR:$Rn), NoItinerary, } def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, so_imm:$a), NoItinerary, - "msr", "\t$mask, $a", - [/* For disassembly only; pattern left blank */]> { + "msr", "\t$mask, $a", []> { bits<5> mask; bits<12> a; diff --git a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp index 752e90af775..0cf9a4a042e 100644 --- a/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ b/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -1430,7 +1430,7 @@ tryParseMSRMaskOperand(SmallVectorImpl &Operands) { // Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf" size_t Start = 0, Next = Mask.find('_'); StringRef Flags = ""; - StringRef SpecReg = Mask.slice(Start, Next); + std::string SpecReg = LowercaseString(Mask.slice(Start, Next)); if (Next != StringRef::npos) Flags = Mask.slice(Next+1, Mask.size()); @@ -1441,7 +1441,7 @@ tryParseMSRMaskOperand(SmallVectorImpl &Operands) { if (SpecReg == "apsr") { FlagsVal = StringSwitch(Flags) - .Case("nzcvq", 0x8) // same as CPSR_c + .Case("nzcvq", 0x8) // same as CPSR_f .Case("g", 0x4) // same as CPSR_s .Case("nzcvqg", 0xc) // same as CPSR_fs .Default(~0U); diff --git a/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp b/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp index c90fe66f262..4a178dc9215 100644 --- a/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp +++ b/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp @@ -481,10 +481,23 @@ void ARMInstPrinter::printMSRMaskOperand(const MCInst *MI, unsigned OpNum, unsigned SpecRegRBit = Op.getImm() >> 4; unsigned Mask = Op.getImm() & 0xf; + // As special cases, CPSR_f, CPSR_s and CPSR_fs prefer printing as + // APSR_nzcvq, APSR_g and APSRnzcvqg, respectively. + if (!SpecRegRBit && (Mask == 8 || Mask == 4 || Mask == 12)) { + O << "APSR_"; + switch (Mask) { + default: assert(0); + case 4: O << "g"; return; + case 8: O << "nzcvq"; return; + case 12: O << "nzcvqg"; return; + } + llvm_unreachable("Unexpected mask value!"); + } + if (SpecRegRBit) - O << "spsr"; + O << "SPSR"; else - O << "cpsr"; + O << "CPSR"; if (Mask) { O << '_'; diff --git a/test/MC/ARM/arm_instructions.s b/test/MC/ARM/arm_instructions.s index 0f93846ce32..5154e559cca 100644 --- a/test/MC/ARM/arm_instructions.s +++ b/test/MC/ARM/arm_instructions.s @@ -121,45 +121,6 @@ @ CHECK: cpsie if, #10 @ encoding: [0xca,0x00,0x0a,0xf1] cpsie if, #10 -@ CHECK: msr cpsr_fc, r0 @ encoding: [0x00,0xf0,0x29,0xe1] - msr apsr, r0 - -@ CHECK: msr cpsr_s, r0 @ encoding: [0x00,0xf0,0x24,0xe1] - msr apsr_g, r0 - -@ CHECK: msr cpsr_f, r0 @ encoding: [0x00,0xf0,0x28,0xe1] - msr apsr_nzcvq, r0 - -@ CHECK: msr cpsr_fs, r0 @ encoding: [0x00,0xf0,0x2c,0xe1] - msr apsr_nzcvqg, r0 - -@ CHECK: msr cpsr_fc, r0 @ encoding: [0x00,0xf0,0x29,0xe1] - msr cpsr_fc, r0 - -@ CHECK: msr cpsr_c, r0 @ encoding: [0x00,0xf0,0x21,0xe1] - msr cpsr_c, r0 - -@ CHECK: msr cpsr_x, r0 @ encoding: [0x00,0xf0,0x22,0xe1] - msr cpsr_x, r0 - -@ CHECK: msr cpsr_fc, r0 @ encoding: [0x00,0xf0,0x29,0xe1] - msr cpsr_fc, r0 - -@ CHECK: msr cpsr_fc, r0 @ encoding: [0x00,0xf0,0x29,0xe1] - msr cpsr_all, r0 - -@ CHECK: msr cpsr_fsx, r0 @ encoding: [0x00,0xf0,0x2e,0xe1] - msr cpsr_fsx, r0 - -@ CHECK: msr spsr_fc, r0 @ encoding: [0x00,0xf0,0x69,0xe1] - msr spsr_fc, r0 - -@ CHECK: msr spsr_fsxc, r0 @ encoding: [0x00,0xf0,0x6f,0xe1] - msr spsr_fsxc, r0 - -@ CHECK: msr cpsr_fsxc, r0 @ encoding: [0x00,0xf0,0x2f,0xe1] - msr cpsr_fsxc, r0 - @ CHECK: add r1, r2, r3, lsl r4 @ encoding: [0x13,0x14,0x82,0xe0] add r1, r2, r3, lsl r4 diff --git a/test/MC/ARM/basic-arm-instructions.s b/test/MC/ARM/basic-arm-instructions.s index a8d09312714..00cfec9c7e6 100644 --- a/test/MC/ARM/basic-arm-instructions.s +++ b/test/MC/ARM/basic-arm-instructions.s @@ -747,6 +747,70 @@ _func: +@------------------------------------------------------------------------------ +@ MSR +@------------------------------------------------------------------------------ + + msr apsr, #5 + msr apsr_g, #5 + msr apsr_nzcvq, #5 + msr APSR_nzcvq, #5 + msr apsr_nzcvqg, #5 + msr cpsr_fc, #5 + msr cpsr_c, #5 + msr cpsr_x, #5 + msr cpsr_fc, #5 + msr cpsr_all, #5 + msr cpsr_fsx, #5 + msr spsr_fc, #5 + msr SPSR_fsxc, #5 + msr cpsr_fsxc, #5 + +@ CHECK: msr CPSR_fc, #5 @ encoding: [0x05,0xf0,0x29,0xe3] +@ CHECK: msr APSR_g, #5 @ encoding: [0x05,0xf0,0x24,0xe3] +@ CHECK: msr APSR_nzcvq, #5 @ encoding: [0x05,0xf0,0x28,0xe3] +@ CHECK: msr APSR_nzcvq, #5 @ encoding: [0x05,0xf0,0x28,0xe3] +@ CHECK: msr APSR_nzcvqg, #5 @ encoding: [0x05,0xf0,0x2c,0xe3] +@ CHECK: msr CPSR_fc, #5 @ encoding: [0x05,0xf0,0x29,0xe3] +@ CHECK: msr CPSR_c, #5 @ encoding: [0x05,0xf0,0x21,0xe3] +@ CHECK: msr CPSR_x, #5 @ encoding: [0x05,0xf0,0x22,0xe3] +@ CHECK: msr CPSR_fc, #5 @ encoding: [0x05,0xf0,0x29,0xe3] +@ CHECK: msr CPSR_fc, #5 @ encoding: [0x05,0xf0,0x29,0xe3] +@ CHECK: msr CPSR_fsx, #5 @ encoding: [0x05,0xf0,0x2e,0xe3] +@ CHECK: msr SPSR_fc, #5 @ encoding: [0x05,0xf0,0x69,0xe3] +@ CHECK: msr SPSR_fsxc, #5 @ encoding: [0x05,0xf0,0x6f,0xe3] +@ CHECK: msr CPSR_fsxc, #5 @ encoding: [0x05,0xf0,0x2f,0xe3] + + msr apsr, r0 + msr apsr_g, r0 + msr apsr_nzcvq, r0 + msr APSR_nzcvq, r0 + msr apsr_nzcvqg, r0 + msr cpsr_fc, r0 + msr cpsr_c, r0 + msr cpsr_x, r0 + msr cpsr_fc, r0 + msr cpsr_all, r0 + msr cpsr_fsx, r0 + msr spsr_fc, r0 + msr SPSR_fsxc, r0 + msr cpsr_fsxc, r0 + +@ CHECK: msr CPSR_fc, r0 @ encoding: [0x00,0xf0,0x29,0xe1] +@ CHECK: msr APSR_g, r0 @ encoding: [0x00,0xf0,0x24,0xe1] +@ CHECK: msr APSR_nzcvq, r0 @ encoding: [0x00,0xf0,0x28,0xe1] +@ CHECK: msr APSR_nzcvq, r0 @ encoding: [0x00,0xf0,0x28,0xe1] +@ CHECK: msr APSR_nzcvqg, r0 @ encoding: [0x00,0xf0,0x2c,0xe1] +@ CHECK: msr CPSR_fc, r0 @ encoding: [0x00,0xf0,0x29,0xe1] +@ CHECK: msr CPSR_c, r0 @ encoding: [0x00,0xf0,0x21,0xe1] +@ CHECK: msr CPSR_x, r0 @ encoding: [0x00,0xf0,0x22,0xe1] +@ CHECK: msr CPSR_fc, r0 @ encoding: [0x00,0xf0,0x29,0xe1] +@ CHECK: msr CPSR_fc, r0 @ encoding: [0x00,0xf0,0x29,0xe1] +@ CHECK: msr CPSR_fsx, r0 @ encoding: [0x00,0xf0,0x2e,0xe1] +@ CHECK: msr SPSR_fc, r0 @ encoding: [0x00,0xf0,0x69,0xe1] +@ CHECK: msr SPSR_fsxc, r0 @ encoding: [0x00,0xf0,0x6f,0xe1] +@ CHECK: msr CPSR_fsxc, r0 @ encoding: [0x00,0xf0,0x2f,0xe1] + @------------------------------------------------------------------------------ @ STM* @------------------------------------------------------------------------------ diff --git a/test/MC/Disassembler/ARM/arm-tests.txt b/test/MC/Disassembler/ARM/arm-tests.txt index 0536eebb317..537ad551a43 100644 --- a/test/MC/Disassembler/ARM/arm-tests.txt +++ b/test/MC/Disassembler/ARM/arm-tests.txt @@ -149,10 +149,10 @@ # CHECK: cpsie if, #10 0xca 0x00 0x0a 0xf1 -# CHECK: msr cpsr_fc, r0 +# CHECK: msr CPSR_fc, r0 0x00 0xf0 0x29 0xe1 -# CHECK: msrmi cpsr_c, #4043309056 +# CHECK: msrmi CPSR_c, #4043309056 0xf1 0xf4 0x21 0x43 # CHECK: rsbs r6, r7, r8 diff --git a/test/MC/Disassembler/ARM/thumb-tests.txt b/test/MC/Disassembler/ARM/thumb-tests.txt index 895a5bb346d..0d55bb795c7 100644 --- a/test/MC/Disassembler/ARM/thumb-tests.txt +++ b/test/MC/Disassembler/ARM/thumb-tests.txt @@ -131,7 +131,7 @@ # CHECK: cpsie aif 0x67 0xb6 -# CHECK: msr cpsr_fc, r0 +# CHECK: msr CPSR_fc, r0 0x80 0xf3 0x00 0x89 # CHECK: blx #-4