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Fixed a case of ARM disassembly getting an assert on a bad encoding

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of a VST instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154544 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Kevin Enderby 2012-04-11 22:40:17 +00:00
parent 056c51e598
commit b318cc16c9
2 changed files with 15 additions and 0 deletions
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2
lib/Target/ARM/Disassembler/ARMDisassembler.cpp
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@ -2410,6 +2410,8 @@ static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn,
case ARM::VST2b8wb_register:
case ARM::VST2b16wb_register:
case ARM::VST2b32wb_register:
if (Rm == 0xF)
return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateImm(0));
break;
case ARM::VST3d8_UPD:

13
test/MC/Disassembler/ARM/invalid-VST1d8Twb_register-thumb.txt Normal file
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@ -0,0 +1,13 @@
# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding}
# Opcode=1839 Name=VST1d8Twb_register Format=ARM_FORMAT_NLdSt(30)
# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
# -------------------------------------------------------------------------------------------------
# | 1: 1: 1: 1| 1: 0: 0: 1| 0: 0: 0: 0| 0: 0: 0: 0| 0: 0: 0: 0| 0: 1: 1: 0| 0: 0: 1: 0| 1: 1: 1: 1|
# -------------------------------------------------------------------------------------------------
#
# A8.6.391 VST1 (multiple single elements)
# This encoding looks like: vst1.8 {d0,d1,d2}, [r0, :128]
# But bits 5-4 for the alignment of 128 encoded as align = 0b10, is available only if <list>
# contains two or four registers. rdar://11220250
0x00 0xf9 0x2f 0x06