From b3235b128f383559a7a9b9119896e406b347879c Mon Sep 17 00:00:00 2001 From: Chad Rosier Date: Fri, 9 Nov 2012 18:25:27 +0000 Subject: [PATCH] Revert r167620; this can be implemented using an existing CL option. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167622 91177308-0d34-0410-b5e6-96231b3b80d8 --- include/llvm/Target/TargetOptions.h | 12 ++++-------- lib/Target/ARM/ARMFastISel.cpp | 12 ++++-------- lib/Target/ARM/ARMISelLowering.cpp | 3 +-- 3 files changed, 9 insertions(+), 18 deletions(-) diff --git a/include/llvm/Target/TargetOptions.h b/include/llvm/Target/TargetOptions.h index 75cfa8c59cb..68ca5678369 100644 --- a/include/llvm/Target/TargetOptions.h +++ b/include/llvm/Target/TargetOptions.h @@ -48,10 +48,10 @@ namespace llvm { UseSoftFloat(false), NoZerosInBSS(false), JITExceptionHandling(false), JITEmitDebugInfo(false), JITEmitDebugInfoToDisk(false), GuaranteedTailCallOpt(false), DisableTailCalls(false), - StackAlignmentOverride(0), RealignStack(true), StrictAlign(false), - EnableFastISel(false), PositionIndependentExecutable(false), - EnableSegmentedStacks(false), UseInitArray(false), TrapFuncName(""), - FloatABIType(FloatABI::Default), AllowFPOpFusion(FPOpFusion::Standard) + StackAlignmentOverride(0), RealignStack(true), EnableFastISel(false), + PositionIndependentExecutable(false), EnableSegmentedStacks(false), + UseInitArray(false), TrapFuncName(""), FloatABIType(FloatABI::Default), + AllowFPOpFusion(FPOpFusion::Standard) {} /// PrintMachineCode - This flag is enabled when the -print-machineinstrs @@ -155,10 +155,6 @@ namespace llvm { /// automatically realigned, if needed. unsigned RealignStack : 1; - /// StrictAlign - This flag indicates that all memory accesses must be - /// aligned. (ARM only) - unsigned StrictAlign : 1; - /// SSPBufferSize - The minimum size of buffers that will receive stack /// smashing protection when -fstack-protection is used. unsigned SSPBufferSize; diff --git a/lib/Target/ARM/ARMFastISel.cpp b/lib/Target/ARM/ARMFastISel.cpp index 7527c8496de..6611862ca07 100644 --- a/lib/Target/ARM/ARMFastISel.cpp +++ b/lib/Target/ARM/ARMFastISel.cpp @@ -1028,8 +1028,7 @@ bool ARMFastISel::ARMEmitLoad(EVT VT, unsigned &ResultReg, Address &Addr, RC = &ARM::GPRRegClass; break; case MVT::i16: - if (Alignment && Alignment < 2 && (!Subtarget->allowsUnalignedMem() || - TM.Options.StrictAlign)) + if (Alignment && Alignment < 2 && !Subtarget->allowsUnalignedMem()) return false; if (isThumb2) { @@ -1044,8 +1043,7 @@ bool ARMFastISel::ARMEmitLoad(EVT VT, unsigned &ResultReg, Address &Addr, RC = &ARM::GPRRegClass; break; case MVT::i32: - if (Alignment && Alignment < 4 && (!Subtarget->allowsUnalignedMem() || - TM.Options.StrictAlign)) + if (Alignment && Alignment < 4 && !Subtarget->allowsUnalignedMem()) return false; if (isThumb2) { @@ -1154,8 +1152,7 @@ bool ARMFastISel::ARMEmitStore(EVT VT, unsigned SrcReg, Address &Addr, } break; case MVT::i16: - if (Alignment && Alignment < 2 && (!Subtarget->allowsUnalignedMem() || - TM.Options.StrictAlign)) + if (Alignment && Alignment < 2 && !Subtarget->allowsUnalignedMem()) return false; if (isThumb2) { @@ -1169,8 +1166,7 @@ bool ARMFastISel::ARMEmitStore(EVT VT, unsigned SrcReg, Address &Addr, } break; case MVT::i32: - if (Alignment && Alignment < 4 && (!Subtarget->allowsUnalignedMem() || - TM.Options.StrictAlign)) + if (Alignment && Alignment < 4 && !Subtarget->allowsUnalignedMem()) return false; if (isThumb2) { diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp index 65cc49e1c33..3b9558bc2a2 100644 --- a/lib/Target/ARM/ARMISelLowering.cpp +++ b/lib/Target/ARM/ARMISelLowering.cpp @@ -9119,8 +9119,7 @@ bool ARMTargetLowering::isDesirableToTransformToIntegerOp(unsigned Opc, bool ARMTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const { // The AllowsUnaliged flag models the SCTLR.A setting in ARM cpus - bool AllowsUnaligned = Subtarget->allowsUnalignedMem() && - !getTargetMachine().Options.StrictAlign; + bool AllowsUnaligned = Subtarget->allowsUnalignedMem(); switch (VT.getSimpleVT().SimpleTy) { default: