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Specify that the high bit of the alignment field is fixed to 0 on these instructions.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143220 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson 2011-10-28 20:43:24 +00:00
parent feaa4c316f
commit b3727fe3ec
1 changed files with 2 additions and 2 deletions
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4
lib/Target/ARM/ARMInstrNEON.td
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@ -389,7 +389,7 @@ multiclass VLD1D3WB<bits<4> op7_4, string Dt> {
"vld1", Dt, "$Vd, $Rn!",
"$Rn.addr = $wb", []> {
let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
let Inst{5-4} = Rn{5-4};
let Inst{4} = Rn{4};
let DecoderMethod = "DecodeVLDInstruction";
let AsmMatchConverter = "cvtVLDwbFixed";
}
@ -397,7 +397,7 @@ multiclass VLD1D3WB<bits<4> op7_4, string Dt> {
(ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1x2u,
"vld1", Dt, "$Vd, $Rn, $Rm",
"$Rn.addr = $wb", []> {
let Inst{5-4} = Rn{5-4};
let Inst{4} = Rn{4};
let DecoderMethod = "DecodeVLDInstruction";
let AsmMatchConverter = "cvtVLDwbRegister";
}