From b3af5de2d97c30355b8109e149326b0664d34085 Mon Sep 17 00:00:00 2001 From: Jim Grosbach Date: Wed, 13 Oct 2010 21:00:04 +0000 Subject: [PATCH] Refactor the ARM 'setend' instruction pattern. Use a single instruction pattern and handle the operand explicitly. Flesh out encoding information. Add an explicit disassembler testcase for the instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116432 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/ARM/ARMInstrFormats.td | 3 +++ lib/Target/ARM/ARMInstrInfo.td | 24 ++++++------------- .../ARM/Disassembler/ARMDisassemblerCore.cpp | 8 +++++-- lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp | 9 +++++++ lib/Target/ARM/InstPrinter/ARMInstPrinter.h | 1 + test/MC/Disassembler/arm-tests.txt | 6 +++++ utils/TableGen/EDEmitter.cpp | 1 + 7 files changed, 33 insertions(+), 19 deletions(-) diff --git a/lib/Target/ARM/ARMInstrFormats.td b/lib/Target/ARM/ARMInstrFormats.td index 49f382df306..68542df58ca 100644 --- a/lib/Target/ARM/ARMInstrFormats.td +++ b/lib/Target/ARM/ARMInstrFormats.td @@ -165,6 +165,9 @@ def s_cc_out : OptionalDefOperand { // ARM special operands for disassembly only. // +def setend_op : Operand { + let PrintMethod = "printSetendOperand"; +} def cps_opt : Operand { let PrintMethod = "printCPSOptionOperand"; diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index 92924ff2b35..17374a92d3d 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -923,24 +923,14 @@ defm PLD : APreLoad<1, 1, "pld">; defm PLDW : APreLoad<1, 0, "pldw">; defm PLI : APreLoad<0, 1, "pli">; -def SETENDBE : AXI<(outs),(ins), MiscFrm, NoItinerary, "setend\tbe", - [/* For disassembly only; pattern left blank */]>, +def SETEND : AXI<(outs),(ins setend_op:$end), MiscFrm, NoItinerary, + "setend\t$end", + [/* For disassembly only; pattern left blank */]>, Requires<[IsARM]> { - let Inst{31-28} = 0b1111; - let Inst{27-20} = 0b00010000; - let Inst{16} = 1; - let Inst{9} = 1; - let Inst{7-4} = 0b0000; -} - -def SETENDLE : AXI<(outs),(ins), MiscFrm, NoItinerary, "setend\tle", - [/* For disassembly only; pattern left blank */]>, - Requires<[IsARM]> { - let Inst{31-28} = 0b1111; - let Inst{27-20} = 0b00010000; - let Inst{16} = 1; - let Inst{9} = 0; - let Inst{7-4} = 0b0000; + bits<1> end; + let Inst{31-10} = 0b1111000100000001000000; + let Inst{9} = end; + let Inst{8-0} = 0; } def DBG : AI<(outs), (ins i32imm:$opt), MiscFrm, NoItinerary, "dbg", "\t$opt", diff --git a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp index a5494091c9f..c73ff6dd59b 100644 --- a/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp +++ b/lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp @@ -2998,13 +2998,17 @@ static bool DisassembleMiscFrm(MCInst &MI, unsigned Opcode, uint32_t insn, case ARM::WFE: case ARM::WFI: case ARM::SEV: - case ARM::SETENDBE: - case ARM::SETENDLE: return true; default: break; } + if (Opcode == ARM::SETEND) { + NumOpsAdded = 1; + MI.addOperand(MCOperand::CreateImm(slice(insn, 9, 9))); + return true; + } + // CPS has a singleton $opt operand that contains the following information: // opt{4-0} = mode from Inst{4-0} // opt{5} = changemode from Inst{17} diff --git a/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp b/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp index 027cdc8cf83..857a3792951 100644 --- a/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp +++ b/lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp @@ -400,6 +400,15 @@ void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum, O << "}"; } +void ARMInstPrinter::printSetendOperand(const MCInst *MI, unsigned OpNum, + raw_ostream &O) { + const MCOperand &Op = MI->getOperand(OpNum); + if (Op.getImm()) + O << "be"; + else + O << "le"; +} + void ARMInstPrinter::printCPSOptionOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O) { const MCOperand &Op = MI->getOperand(OpNum); diff --git a/lib/Target/ARM/InstPrinter/ARMInstPrinter.h b/lib/Target/ARM/InstPrinter/ARMInstPrinter.h index d82e56863e6..d707706063a 100644 --- a/lib/Target/ARM/InstPrinter/ARMInstPrinter.h +++ b/lib/Target/ARM/InstPrinter/ARMInstPrinter.h @@ -87,6 +87,7 @@ public: void printT2AddrModeSoRegOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); + void printSetendOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); void printCPSOptionOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); void printMSRMaskOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); void printNegZeroOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O); diff --git a/test/MC/Disassembler/arm-tests.txt b/test/MC/Disassembler/arm-tests.txt index 0b4c2978fe3..6595fede1cc 100644 --- a/test/MC/Disassembler/arm-tests.txt +++ b/test/MC/Disassembler/arm-tests.txt @@ -109,3 +109,9 @@ # CHECK: usat r8, #0, r10, asr #32 0x5a 0x80 0xe0 0xe6 + +# CHECK: setend be +0x00 0x02 0x01 0xf1 + +# CHECK: setend le +0x00 0x00 0x01 0xf1 diff --git a/utils/TableGen/EDEmitter.cpp b/utils/TableGen/EDEmitter.cpp index a4cac555c05..8435bb4144d 100644 --- a/utils/TableGen/EDEmitter.cpp +++ b/utils/TableGen/EDEmitter.cpp @@ -567,6 +567,7 @@ static int ARMFlagFromOpName(LiteralConstantEmitter *type, IMM("jtblock_operand"); IMM("nohash_imm"); IMM("cpinst_operand"); + IMM("setend_op"); IMM("cps_opt"); IMM("vfp_f64imm"); IMM("vfp_f32imm");